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PRELIMINARY INVERSE MULTIPLEXING OVER ATM DATA SHEET PMC-2001723 ISSUE 3
PM7340 S/UNI-IMA-8
INVERSE MULTIPLEXING OVER ATM
PM7340
S/UNI-IMA-8
S/UNI INVERSE MULTIPLEXING FOR ATM, 8 LINKS
DATA SHEET
PROPRIETARY AND CONFIDENTIAL PRELIMINARY ISSUE 3: FEBUARY, 2001
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
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PRELIMINARY INVERSE MULTIPLEXING OVER ATM DATA SHEET PMC-2001723 ISSUE 3
PM7340 S/UNI-IMA-8
INVERSE MULTIPLEXING OVER ATM
CONTENTS 1 2 3 4 5 DEFINITIONS .......................................................................................... 1 FEATURES .............................................................................................. 3 APPLICATIONS ....................................................................................... 8 REFERENCES......................................................................................... 9 APPLICATION EXAMPLES ................................................................... 10 5.1 5.2 6 7 8 9 MULTI-SERVICE ACCESS - IADS, ACCESS CONCENTRATORS .................................................................................................... 10 REMOTE DSLAM WAN UPLINK................................................. 10
BLOCK DIAGRAM ................................................................................. 12 DESCRIPTION....................................................................................... 13 PIN DIAGRAM ....................................................................................... 15 PIN DESCRIPTION................................................................................ 16 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 RECEIVE SLAVE ATM INTERFACE (UTOPIA L2 MODE) (26 SIGNALS).................................................................................... 18 TRANSMIT SLAVE INTERFACE (ANY-PHY MODE) (30 SIGNALS)21 TRANSMIT SLAVE INTERFACE (UTOPIA L2 MODE) (26 SIGNALS).................................................................................... 24 MICROPROCESSOR INTERFACE (31 SIGNALS)..................... 26 SDRAM I/F (35 SIGNALS) .......................................................... 28 CLK/DATA (33 SIGNALS)............................................................ 31 GENERAL (5 SIGNALS) ............................................................. 35 JTAG & SCAN INTERFACE (7 SIGNALS) .................................. 37
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PRELIMINARY INVERSE MULTIPLEXING OVER ATM DATA SHEET PMC-2001723 ISSUE 3
PM7340 S/UNI-IMA-8
INVERSE MULTIPLEXING OVER ATM
9.9 10
POWER (120 SIGNALS) ............................................................. 38
FUNCTIONAL DESCRIPTION............................................................... 41 10.1 ANY-PHY/UTOPIA INTERFACE.................................................. 41 10.1.1 TRANSMIT ANY-PHY/UTOPIA SLAVE (TXAPS).............. 41 10.1.2 RECEIVE ANY-PHY/UTOPIA SLAVE (RXAPS)................ 44 10.1.3 SUMMARY OF ANY-PHY/UTOPIA MODES ..................... 49 10.1.4 ANY-PHY/UTOPIA LOOPBACK ....................................... 50 10.2 IMA SUB-LAYER ......................................................................... 50 10.2.1 OVERVIEW ...................................................................... 50 10.2.2 IDCC SCHEDULER.......................................................... 51 10.2.3 TRANSMIT IMA PROCESSOR (TIMA) ............................ 52 10.2.4 RECEIVE IMA DATA PROCESSOR (RDAT) .................... 56 10.2.5 LINK/GROUP STATE MACHINES ................................... 69 10.2.6 SUPPORT OF IMA TEST PATTERN PROCEDURE ........ 80 10.2.7 SUPPORT OF SYMMETRIC/ASYMMETRIC OPERATION MODES .......................................................................... 80 10.2.8 SUPPORT OF DIFFERENT IMA VERSIONS................... 80 10.2.9 SDRAM INTERFACE........................................................ 81 10.3 10.4 LINK FIFOS................................................................................. 84 TC LAYER ................................................................................... 85 10.4.1 TX TC LAYER (TTTC) ...................................................... 85 10.4.2 RX TC LAYER (RTTC)...................................................... 85 10.5 LINE SIDE PHYSICAL LAYER .................................................... 87
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PRELIMINARY INVERSE MULTIPLEXING OVER ATM DATA SHEET PMC-2001723 ISSUE 3
PM7340 S/UNI-IMA-8
INVERSE MULTIPLEXING OVER ATM
10.5.1 TX CLOCK/DATA (TCAS)................................................. 87 10.5.2 RX CLOCK/DATA (RCAS) ................................................ 88 10.6 MICROPROCESSOR INTERFACE ............................................ 89 10.6.1 MAPPING AND LINK IDENTIFICATION........................... 89 10.6.2 INTERRUPT DRIVEN ERROR/STATUS REPORTING .... 90 10.6.3 REGISTERS..................................................................... 91 11 NORMAL MODE REGISTER DESCRIPTION ....................................... 97 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 GLOBAL AND INTERRUPT REGISTERS................................... 98 MASTER INTERRUPT INTERFACE ......................................... 102 UTOPIA INTERFACE REGISTERS ........................................... 111 SDRAM CONFIGURATION AND DIAGNOSTIC ACCESS ........118 TC LAYER REGISTERS ........................................................... 125 LINE CLOCK/DATA INTERFACE .............................................. 135 RIPP REGISTERS .................................................................... 149 RDAT REGISTERS ................................................................... 215 TIMA REGISTERS .................................................................... 241
11.10 TX IDCC REGISTERS .............................................................. 252 11.11 RX IDCC REGISTERS .............................................................. 254 12 OPERATION ........................................................................................ 258 12.1 12.2 12.3 HARDWARE CONFIGURATION............................................... 258 START-UP ................................................................................. 258 CONFIGURING THE S/UNI-IMA-8............................................ 259
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PRELIMINARY INVERSE MULTIPLEXING OVER ATM DATA SHEET PMC-2001723 ISSUE 3
PM7340 S/UNI-IMA-8
INVERSE MULTIPLEXING OVER ATM
12.3.1 CONFIGURING CLOCK/DATA INTERFACE .................. 259 12.3.2 CONFIGURING TC LAYER OPTIONS ........................... 261 12.3.3 UTOPIA INTERFACE CONFIGURATION....................... 261 12.4 IMA_LAYER CONFIGURATION................................................ 262 12.4.1 INDIRECT ACCESS TO INTERNAL MEMORY TABLES 262 12.4.2 CONFIGURING LINKS FOR TRANSMISSION CONVERGENCE OPERATIONS ................................. 263 12.4.3 CONFIGURING FOR IMA OPERATIONS ...................... 264 12.5 IMA OPERATIONS .................................................................... 267 12.5.1 ISSUING A RIPP COMMAND......................................... 268 12.5.2 SUMMARY OF RIPP COMMANDS ................................ 269 12.5.3 ADDING A GROUP......................................................... 275 12.5.4 DELETING A GROUP..................................................... 276 12.5.5 RESTART GROUP ......................................................... 276 12.5.6 INHIBIT GROUP/NOT INHIBIT GROUP......................... 277 12.5.7 ADDING A LINK OR LINKS TO AN EXISTING GROUP (START LASR) ............................................................. 277 12.5.8 REPORTING LINK DEFECTS IN THE ICP CELL .......... 278 12.5.9 FAULTING/INHIBITING LINKS ...................................... 278 12.5.10 CHANGE TRL .............................................................. 278 12.5.11 DELETING A LINK FROM A GROUP ........................... 279 12.5.12 TEST PATTERN PROCEDURES ................................. 279 12.5.13 IMA EVENTS ................................................................ 279
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PRELIMINARY INVERSE MULTIPLEXING OVER ATM DATA SHEET PMC-2001723 ISSUE 3
PM7340 S/UNI-IMA-8
INVERSE MULTIPLEXING OVER ATM
12.5.14 END-TO-END CHANNEL COMMUNICATION ............. 280 12.6 DIAGNOSTIC FEATURES ........................................................ 280 12.6.1 ICP CELL TRACE........................................................... 280 12.6.2 SDRAM DIAGNOSTIC ACCESS .................................... 281 12.7 13 IMA PERFORMANCE PARAMETERS AND FAILURE ALARMS SUPPORT ................................................................................. 282
FUNCTIONAL TIMING......................................................................... 286 13.1 13.2 13.3 RECEIVE LINK INPUT TIMING................................................. 286 TRANSMIT LINK OUTPUT TIMING .......................................... 287 ANY-PHY/UTOPIA L2 INTERFACES ........................................ 290 13.3.1 UTOPIA L2 TRANSMIT SLAVE INTERFACE ................. 290 13.3.2 ANY-PHY TRANSMIT SLAVE INTERFACE.................... 291 13.3.3 UTOPIA L2 MULTI-PHY RECEIVE SLAVE INTERFACE 292 13.3.4 UTOPIA L2 SINGLE-PHY RECEIVE SLAVE INTERFACE ..................................................................................... 293 13.3.5 ANY-PHY RECEIVE SLAVE INTERFACE ...................... 294 13.4 SDRAM INTERFACE ................................................................ 294
14 15 16
ABSOLUTE MAXIMUM RATINGS ....................................................... 299 D. C. CHARACTERISTICS .................................................................. 300 A.C. TIMING CHARACTERISTICS...................................................... 303 16.1 16.2 16.3 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS .................................................................................................. 303 SYNCHRONOUS I/O TIMING................................................... 307 JTAG TIMING .............................................................................311
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PRELIMINARY INVERSE MULTIPLEXING OVER ATM DATA SHEET PMC-2001723 ISSUE 3
PM7340 S/UNI-IMA-8
INVERSE MULTIPLEXING OVER ATM
17 18
ORDERING AND THERMAL INFORMATION...................................... 313 MECHANICAL INFORMATION ............................................................ 314
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
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PRELIMINARY INVERSE MULTIPLEXING OVER ATM DATA SHEET PMC-2001723 ISSUE 3
PM7340 S/UNI-IMA-8
INVERSE MULTIPLEXING OVER ATM
LIST OF FIGURES FIGURE 1 - MULTI-SERVICE ACCESS - IADS AND ACCESS CONCENTRATORS. ......................................................................... 10 FIGURE 2 -S/UNI-IMA-8 IN A REMOTE DSLAM WAN UPLINK APPLICATION.11 FIGURE 3 - S/UNI-IMA-8 BLOCK DIAGRAM.................................................. 12 FIGURE 4 - S/UNI-IMA PRELIMINARY PINOUT (BOTTOM VIEW) ............... 15 FIGURE 5 - 16-BIT TRANSMIT CELL TRANSFER FORMAT ......................... 43 FIGURE 6 - 8-BIT TRANSMIT CELL TRANSFER FORMAT ........................... 44 FIGURE 7 - 16-BIT RECEIVE CELL TRANSFER FORMAT ........................... 47 FIGURE 8 - 8-BIT RECEIVE CELL TRANSFER FORMAT ............................. 48 FIGURE 9 - INVERSE MULTIPLEXING .......................................................... 51 FIGURE 10 - IFSM STATE MACHINE .............................................................. 58 FIGURE 11 - STUFF EVENT WITH ERRORED ICP (ADVANCED INDICATION) 60 FIGURE 12 - INVALID STUFF SEQUENCE (ADVANCED INDICATION) ......... 60 FIGURE 13 - ERRORED/INVALID ICP CELLS IN PROXIMITY TO A STUFF EVENT............................................................................................... 61 FIGURE 14 - SNAPSHOT OF DCB BUFFERS................................................. 62 FIGURE 15 - SNAPSHOT OF DCB BUFFERS AFTER ADDITION OF LINK WITH SMALLER TRANSPORT DELAY....................................................... 63 FIGURE 16 - SNAPSHOT OF DCB BUFFERS WHEN TRYING TO ADD LINK WITH LARGER TRANSPORT DELAY............................................... 64 FIGURE 17 - SNAPSHOT OF DCB BUFFERS AFTER DELAY ADJUSTMENT 65
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PRELIMINARY INVERSE MULTIPLEXING OVER ATM DATA SHEET PMC-2001723 ISSUE 3
PM7340 S/UNI-IMA-8
INVERSE MULTIPLEXING OVER ATM
FIGURE 18 - SNAPSHOT OF DCB BUFFERS AFTER DELETION OF LINKS FROM GROUP .................................................................................. 66 FIGURE 19 - IMA ERROR/MAINTENANCE STATE DIAGRAM ........................ 67 FIGURE 20 - CELL STORAGE MAP................................................................. 82 FIGURE 21 - 2 MBYTE ..................................................................................... 83 FIGURE 22 - 8 MBYTE ..................................................................................... 83 FIGURE 23 - CELL DELINEATION STATE DIAGRAM...................................... 86 FIGURE 24 -BURST RAM FORMAT............................................................... 121 FIGURE 25 - UNCHANNELIZED RECEIVE LINK TIMING ............................. 286 FIGURE 26 - CHANNELIZED T1 RECEIVE LINK TIMING ............................. 287 FIGURE 27 - CHANNELIZED E1 RECEIVE LINK TIMING ............................. 287 FIGURE 28 - UNCHANNELIZED TRANSMIT LINK TIMING........................... 288 FIGURE 29 - CHANNELIZED T1 TRANSMIT LINK TIMING W/ CLOCK GAPPED LOW ................................................................................................ 288 FIGURE 30 - CHANNELIZED T1 TRANSMIT LINK TIMING W/ CLOCK GAPPED HIGH................................................................................................ 289 FIGURE 31 - CHANNELIZED E1 TRANSMIT LINK TIMING W/ CLOCK GAPPED LOW ................................................................................................ 289 FIGURE 32 - CHANNELIZED E1 TRANSMIT LINK TIMING W/ CLOCK GAPPED HOW ................................................................................................ 289 FIGURE 33 - UTOPIA L2 TRANSMIT SLAVE ................................................. 291 FIGURE 34 - ANY-PHY TRANSMIT SLAVE .................................................... 292 FIGURE 35 - UTOPIA L2 MULTI-PHY RECEIVE SLAVE................................ 293 FIGURE 36 - UTOPIA L2 SINGLE-PHY RECEIVE SLAVE ............................. 293 FIGURE 37 - ANY-PHY RECEIVE SLAVE ...................................................... 294
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PRELIMINARY INVERSE MULTIPLEXING OVER ATM DATA SHEET PMC-2001723 ISSUE 3
PM7340 S/UNI-IMA-8
INVERSE MULTIPLEXING OVER ATM
FIGURE 38 - SDRAM READ TIMING ............................................................. 295 FIGURE 39 - SDRAM WRITE TIMING............................................................ 296 FIGURE 40 - SDRAM REFRESH.................................................................... 297 FIGURE 41 - POWER UP AND INITIALIZATION SEQUENCE....................... 298 FIGURE 42 - MICROPROCESSOR INTERFACE READ TIMING .................. 304 FIGURE 43 - MICROPROCESSOR INTERFACE WRITE TIMING ................. 306 FIGURE 44 - RSTB TIMING............................................................................ 307 FIGURE 45 - SYNCHRONOUS I/O TIMING ................................................... 307 FIGURE 46 - JTAG PORT INTERFACE TIMING ............................................ 312
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PRELIMINARY INVERSE MULTIPLEXING OVER ATM DATA SHEET PMC-2001723 ISSUE 3
PM7340 S/UNI-IMA-8
INVERSE MULTIPLEXING OVER ATM
LIST OF TABLES TABLE 1 REVISION HISTORY......................................................................... 2 TABLE 2 TABLE 3 TABLE 4 TABLE 5 TABLE 6 TABLE 7 TABLE 8 TABLE 9 TABLE 10 TERMINOLOGY ............................................................................... 1 UTOPIA L2 AND ANY-PHY COMPARISON .................................... 45 PM COMMAND DESCRIPTION .................................................... 70 REGISTER MEMORY MAP............................................................ 91 CONFIGURATION MEMORY ADDRESS SPACE ........................ 150 CONTEXT MEMORY ADDRESS SPACE..................................... 151 RIPP GROUP CONFIGURATION RECORD STRUCTURE ........ 152 RX PHYSICAL LINK TABLE ....................................................... 159 RIPP TX LINK CONFIGURATION RECORD STRUCTURE....... 160
TABLE 11 RIPP RX LINK CONFIGURATION RECORD STRUCTURE ....... 162 TABLE 12 RIPP GROUP CONTEXT RECORD STRUCTURE ..................... 163 TABLE 13 RIPP TX LINK CONTEXT RECORD STRUCTURE..................... 175 TABLE 14 RIPP RX LINK CONTEXT RECORD STRUCTURE .................... 178 TABLE 15 COMMAND REGISTER ENCODING .......................................... 195 TABLE 16 COMMAND DATA REGISTER ARRAY FORMAT ........................ 203 TABLE 17 GROUP ERROR/STATUS BIT MAPPING ................................... 204 TABLE 18 LINK EVENT INTERRUPT BIT MAPPING................................... 207 TABLE 19 LINK STATUS BIT MAPPING ...................................................... 209 TABLE 20 RECEIVE ICP CELL BUFFER STRUCTURE .............................. 213 TABLE 21 RDAT LINK STATISTICS RECORD (IMA) ................................... 219
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PRELIMINARY INVERSE MULTIPLEXING OVER ATM DATA SHEET PMC-2001723 ISSUE 3
PM7340 S/UNI-IMA-8
INVERSE MULTIPLEXING OVER ATM
TABLE 22 RDAT LINK STATISTICS RECORD (TC)..................................... 220 TABLE 23 RDAT IMA GROUP STATISTICS RECORD................................. 221 TABLE 24 RDAT TC GROUP STATISTICS RECORD .................................. 222 TABLE 25 RDAT VALIDATION RECORD ..................................................... 222 TABLE 26 RDAT LINK CONTEXT RECORD ................................................ 225 TABLE 27 RECEIVE ICP CELL BUFFER STRUCTURE .............................. 230 TABLE 28 RDAT IMA GROUP CONTEXT RECORD.................................... 232 TABLE 29 RDAT TC CONTEXT RECORD ................................................... 233 TABLE 30 RECEIVE ATM CONGESTION COUNT REGISTER ................... 233 TABLE 31 TRANSMIT IMA GROUP CONTEXT RECORD ........................... 244 TABLE 32 TRANSMIT GROUP CONFIGURATION TABLE RECORD ........... 247 TABLE 33 TRANSMIT LID TO PHYSICAL LINK MAPPING TABLE ............. 248 TABLE 34 TIMA PHYSICAL LINK CONTEXT RECORD............................... 248 TABLE 35 260 TABLE 36 IMA PERFORMANCE PARAMETER SUPPORT......................... 282 TABLE 37 IMA FAILURE ALARM SUPPORT ............................................... 284 TABLE 38 ABSOLUTE MAXIMUM RATINGS............................................... 299 TABLE 39 D.C. CHARACTERISTICS ........................................................... 300 TABLE 40 MICROPROCESSOR INTERFACE READ ACCESS................... 303 TABLE 41 MICROPROCESSOR INTERFACE WRITE ACCESS ................. 305 TABLE 42 RTSB TIMING .............................................................................. 306 TABLE 43 SYSCLK AND REFCLK TIMING.................................................. 307
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PRELIMINARY INVERSE MULTIPLEXING OVER ATM DATA SHEET PMC-2001723 ISSUE 3
PM7340 S/UNI-IMA-8
INVERSE MULTIPLEXING OVER ATM
TABLE 44 CELL BUFFER SDRAM INTERFACE.......................................... 307 TABLE 45 ANY-PHY/UTOPIA TRANSMIT INTERFACE ............................... 308 TABLE 46 ANY-PHY/UTOPIA RECEIVE INTERFACE ................................. 308 TABLE 47 SERIAL LINK INPUT.................................................................... 309 TABLE 48 SERIAL LINK OUTPUT................................................................ 310 TABLE 49 JTAG PORT INTERFACE .............................................................311 TABLE 50 ORDERING AND THERMAL INFORMATION.............................. 313 TABLE 51 THERMAL INFORMATION - THETA JA VS. AIRFLOW ............... 313
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PRELIMINARY INVERSE MULTIPLEXING OVER ATM DATA SHEET PMC-2001723 ISSUE 3
PM7340 S/UNI-IMA-8
INVERSE MULTIPLEXING OVER ATM
LIST OF REGISTERS REGISTER 0X000: GLOBAL RESET ............................................................... 98 REGISTER 0X002: GLOBAL CONFIGURATION ............................................. 99 REGISTER 0X004: JTAG ID (MSB)................................................................ 101 REGISTER 0X006: JTAG ID (LSB)................................................................. 101 REGISTER 0X008: MASTER INTERRUPT REGISTER................................. 102 REGISTER 0X00A: MISCELLANEOUS INTERRUPT REGISTER................. 104 REGISTER 0X00C: TC INTERRUPT FIFO .................................................... 106 REGISTER 0X010: MASTER INTERRUPT ENABLE REGISTER ................. 108 REGISTER 0X012: MISCELLANEOUS INTERRUPT ENABLE REGISTER .. 109 REGISTER 0X014: TC INTERRUPT ENABLE REGISTER.............................110 REGISTER 0X020: TRANSMIT ANY-PHY/UTOPIA CELL AVAILABLE ENABLE 111 REGISTER 0X022: RECEIVE UTOPIA CELL AVAILABLE ENABLE ...............112 REGISTER 0X024: RECEIVE ANY-PHY/UTOPIA CONFIG REG (RXAPS_CFG) 113 REGISTER 0X026: TRANSMIT ANY-PHY/UTOPIA CONFIG REG (TXAPS_CFG)115 REGISTER 0X028: TRANSMIT ANY-PHY ADDRESS CONFIG REGISTER (TXAPS_ADD_CFG) ........................................................................117 REGISTER 0X040: SDRAM CONFIGURATION .............................................118 REGISTER 0X042 SDRAM DIAGNOSTICS....................................................119 REGISTER 0X044: SDRAM DIAG BURST RAM INDIRECT ACCESS .......... 120 REGISTER 0X046: SDRAM DIAG INDIRECT BURST RAM DATA LSB ........ 121
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PRELIMINARY INVERSE MULTIPLEXING OVER ATM DATA SHEET PMC-2001723 ISSUE 3
PM7340 S/UNI-IMA-8
INVERSE MULTIPLEXING OVER ATM
REGISTER 0X048: SDRAM DIAG INDIRECT BURST RAM DATA MSB ....... 121 REGISTER 0X04A: SDRAM DIAG WRITE CMD 1 ........................................ 123 REGISTER 0X04C: SDRAM DIAG WRITE CMD 2 ........................................ 123 REGISTER 0X04E: SDRAM DIAG READ CMD 1 .......................................... 124 REGISTER 0X050: SDRAM DIAG READ CMD 2 .......................................... 124 REGISTER 0X060: TTTC INDIRECT STATUS............................................... 125 REGISTER 0X062: TTTC INDIRECT LINK DATA REGISTER #1 .................. 126 REGISTER 0X070: RTTC INDIRECT LINK STATUS ..................................... 127 REGISTER 0X072: RTTC INDIRECT LINK DATA REGISTER #1 .................. 129 REGISTER 0X074: RTTC INDIRECT LINK DATA REGISTER #2 .................. 132 REGISTER 0X076: RTTC INDIRECT LINK DATA REGISTER #3 .................. 134 REGISTER 0X078: LCD COUNT THRESHOLD ............................................ 135 REGISTER 0X100: RCAS INDIRECT LINK AND TIME-SLOT SELECT ........ 135 REGISTER 0X102: RCAS INDIRECT LINK DATA ......................................... 137 REGISTER 0X104: RCAS FRAMING BIT THRESHOLD ............................... 139 REGISTER 0X106: RCAS LINK DISABLE ..................................................... 140 REGISTER 0X140- 0X14E: RCAS LINK #0 TO LINK #7 CONFIGURATION . 141 REGISTER 0X180: TCAS INDIRECT LINK AND TIME-SLOT SELECT......... 142 REGISTER 0X182: TCAS INDIRECT CHANNEL DATA ................................. 144 REGISTER 0X184: FRAMING BIT THRESHOLD .......................................... 145 REGISTER 0X186: TCAS IDLE TIME-SLOT FILL DATA................................ 146 REGISTER 0X188: TCAS CHANNEL DISABLE REGISTER ......................... 147
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PRELIMINARY INVERSE MULTIPLEXING OVER ATM DATA SHEET PMC-2001723 ISSUE 3
PM7340 S/UNI-IMA-8
INVERSE MULTIPLEXING OVER ATM
REGISTER 0X1C0 - 0X1CE: TCAS LINK #0 TO LINK #7 CONFIGURATION148 REGISTER 0X200:RIPP CONTROL .............................................................. 149 REGISTER 0X202:RIPP INDIRECT MEMORY ACCESS CONTROL ............ 150 REGISTER 0X204 - 0X206:RIPP INDIRECT MEMORY DATA REGISTER ARRAY............................................................................................. 152 REGISTER 0X20C: RIPP TIMER TICK CONFIGURATION REGISTER ........ 185 REGISTER 0X20E: GROUP TIMEOUT REGISTER # 1 ................................ 186 REGISTER 0X210: GROUP TIMEOUT REGISTER # 2 ................................. 187 REGISTER 0X212: TX LINK TIMEOUT REGISTER ...................................... 188 REGISTER 0X214: RX LINK TIMEOUT REGISTER ...................................... 189 REGISTER 0X216: RIPP INTERRUPT STATUS REGISTER......................... 190 REGISTER 0X218:RIPP GROUP INTERRUPT ENABLE REGISTER ........... 191 REGISTER 0X21A:RIPP TX LINK INTERRUPT ENABLE REGISTER .......... 192 REGISTER 0X21C:RIPP RX LINK INTERRUPT ENABLE REGISTER.......... 193 REGISTER 0X220-22C: RIPP COMMAND REGISTER ................................. 194 REGISTER 0X22E: COMMAND READ DATA CONTROL REGISTER........... 198 REGISTER 0X230: ICP CELL FORWARDING STATUS REGISTER ............. 199 REGISTER 0X232: ICP CELL FORWARDING CONTROL REGISTER ......... 200 REGISTER 0X240- 0X29E:RIPP COMMAND DATA REGISTER ARRAY ...... 201 REGISTER 0X2C0- 0X2FE: FORWARDING ICP CELL BUFFER.................. 212 REGISTER 0X300: RDAT INDIRECT MEMORY COMMAND ........................ 215 REGISTER 0X302: RDAT INDIRECT MEMORY ADDRESS .......................... 217 REGISTER 0X304: RDAT INDIRECT MEMORY DATA LSB .......................... 218
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PRELIMINARY INVERSE MULTIPLEXING OVER ATM DATA SHEET PMC-2001723 ISSUE 3
PM7340 S/UNI-IMA-8
INVERSE MULTIPLEXING OVER ATM
REGISTER 0X306: RDAT INDIRECT MEMORY DATA MSB ......................... 219 REGISTER 0X308: RDAT CONFIGURATION ................................................ 234 REGISTER 0X30A: RECEIVE ATM CONGESTION STATUS ........................ 236 REGISTER 0X30E: RECEIVE TC OVERRUN STATUS ................................. 237 REGISTER 0X310: RDAT MASTER INTERRUPT STATUS ........................... 238 REGISTER 0X312: RECEIVE ATM CONGESTION INTERRUPT ENABLE... 239 REGISTER 0X316: RDAT MASTER INTERRUPT ENABLE .......................... 240 REGISTER 0X320: TIMA INDIRECT MEMORY COMMAND ......................... 241 REGISTER 0X322: TIMA INDIRECT MEMORY ADDRESS ........................... 242 REGISTER 0X324: TIMA INDIRECT MEMORY DATA LSB............................ 243 REGISTER 0X326: TIMA INDIRECT MEMORY DATA MSB........................... 244 REGISTER 0X328 TX LINK FIFO OVERFLOW STATUS .............................. 251 REGISTER 0X336 INTERRUPT ENABLE...................................................... 252 REGISTER 0X340: TXIDCC INDIRECT LINK ACCESS................................. 252 REGISTER 0X342: TXIDCC INDIRECT LINK DATA REGISTER 1 ................ 254 REGISTER 0X350: RXIDCC INDIRECT LINK ACCESS ................................ 254 REGISTER 0X352: RXIDCC INDIRECT LINK DATA REGISTER 1................ 256 REGISTER 0X366: DLL CONTROL STATUS................................................. 257
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PRELIMINARY INVERSE MULTIPLEXING OVER ATM DATA SHEET PMC-2001723 ISSUE 3
PM7340 S/UNI-IMA-8
INVERSE MULTIPLEXING OVER ATM
1
DEFINITIONS Table 2 Term Any-PHY ATM CDV CTC DLL ECBI FIFO Framed HEC HCS ICP IDCC IDCR IFSN IMA ITC LCD LID LSI MIB MCFD OAM Terminology Definition Interoperable version of UTOPIA and UTOPIA L2, with inband addressing. Asynchronous Transfer Mode Cell Delay Variation Common Transmit Clock Delay Locked Loop Enhanced Common Bus Interface (asynchronous register bus and interface) First-In-First-Out Framing information available - may be channelized or unchannelized. Header Error Check Header Check Sequence IMA Control Protocol Cell IMA Data Cell Clock IMA Data Cell Rate IMA Frame Sequence Number Inverse Multiplexing for ATM Independent Transmit Clock Loss of Cell Delineation Link ID Link Stuff Indication Management Information Base Multi-Channel Cell Based FIFO Operation, Administration and Maintenance
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PRELIMINARY INVERSE MULTIPLEXING OVER ATM DATA SHEET PMC-2001723 ISSUE 3
PM7340 S/UNI-IMA-8
INVERSE MULTIPLEXING OVER ATM
OCD PISO PM RCAS RDAT RIPP RMTS SIPO SPE TC TCAS TDM TRL TRLCR TSB TC TIMA Unframed UTOPIA
Out of Cell Delineation Parallel in Serial Out Plane Management Receive Channel Assigner RX IMA Data Processor RX IMA Protocol Processor RX Master TX Slave Serial in Parallel Out Synchronous Payload Envelope Transmission Convergence Transmit Channel Assigner Time Division Multiplexing Timing Reference Link TRL Cell Rate Telecom Systems Block Transmission Convergence TX IMA Processor No framing information available Universal Test & Operations PHY Interface for ATM
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PRELIMINARY INVERSE MULTIPLEXING OVER ATM DATA SHEET PMC-2001723 ISSUE 3
PM7340 S/UNI-IMA-8
INVERSE MULTIPLEXING OVER ATM
2
FEATURES The PM7340 S/UNI-IMA-8 is a monolithic integrated circuit that implements the Inverse Multiplexing for ATM (IMA 1.1) protocol with backward compatibility to IMA 1.0 and the Transmission Convergence (TC) layer function. The S/UNIIMA-8 supports 8 T1, E1 or unchannelized links where each link is dynamically configurable to support either IMA 1.1, backward compatible IMA 1.0, ATM over T1/E1, ATM over fractional T1/E1 or ATM HEC cell delination for unchannelized links Unchannelized links may be used to support applications such as ADSL. Standards Supported * * ATM Forum Inverse Multiplexing for ATM Specification Version 1.1, March 1999 ATM Forum Inverse Multiplexing for ATM Specification Version 1.0 - supports the method of reporting Rx cell information as in Appendix C.8 of the ATM Forum Inverse Multiplexing for ATM Specification Version 1.1 for symmetrical configurations with M=128. I.432-1 B-ISDN user network interface - Physical Layer specification: General characteristics I.432-3 B-ISDN user network interface - Physical Layer specification: 1544 kbps and 2048 kbps operation ATM on Fractional E1/T1, af-phy-0130.00 October, 1999
* * *
IMA Features * * * * * IMA 1.1 protocol including group and link state machines implemented by onchip hardware. Supports up to 4 simultaneous IMA groups. Each IMA group can support any number of supported links. Each link can be programmed for either IMA processing or cell delineation. Supports all IMA Group Symmetry modes: * Symmetrical configuration with symmetrical operation
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PRELIMINARY INVERSE MULTIPLEXING OVER ATM DATA SHEET PMC-2001723 ISSUE 3
PM7340 S/UNI-IMA-8
INVERSE MULTIPLEXING OVER ATM
* * * * * * * * *
Symmetrical configuration with asymmetrical operation. Asymmetrical configuration with asymmetrical operation.
Performs IMA differential delay calculation and synchronization. Provides programmable limit on allowable differential delay and minimum number of links per group. Supports up to 279 ms (for T1 links) and 226 ms (for E1 links) link-differential delay between links in an IMA group. Performs ICP and stuff-cell insertion and removal. Supports both Common Transmit Clock (CTC) and Independent Transmit Clock (ITC) transmit ICP stuffing modes. Supports IMA frame length (M) equal to 32, 64, 128, or 256. Optionally supports the IMA 1.0 method of reporting Rx cell information as defined in appendix C.8 of the ATM Forum Inverse Multiplexing for ATM Specification Version 1.1 for symmetrical configurations with M=128. Provides IMA layer statistic counts and alarms for support of IMA Performance and Failure Alarm Monitoring and MIB support. Provides per link counters for statistics and performance monitoring: * * * * * * ICP Violations OIF anomalies Rx Link stuff events Tx Link stuff events User cells Filler cells
* *
*
Provides per group counters for statistics and performance monitoring: * User cells received
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* * *
Filler cells received User cells transmitted Filler cells transmitted
TC Features * * * * Performs cell delineation on all links. Performs receive cell Header Error Check (HEC) checking and transmit cell HEC generation. Optionally supports receive cell payload unscrambling and transmit cell payload scrambling. Provides TC layer statistics counts and alarms for MIB support.
Interface Support * * * * * * * * Supports 8 individual serial T1, E1 or unchannelized links via a 2-pin clock and data interface. Supports ATM over fractional T1/E1 by providing the capability to select any DS0 timeslots that are active in a link. Serial link interface supports both independent transmit clock (ITC) and common transmit clock (CTC) options. Interfaces to a 1M x 16 SDRAM for 279 msec of T1, 226 msec of E1 differential delay tolerance through a 16-bit SDRAM interface. Provides a 16-bit microprocessor bus interface for configuration and Link and Unit Management. ATM receive interface supports 8- and 16-bit UTOPIA L2 or Any-PHY cell interfaces at clock rates up to 52 MHz. Any-PHY receive slave appears as a single device. The PHY-ID of each cell is identified in the in-band address. UTOPIA L2 receive slave appears as a 31 port multi-PHY.
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PRELIMINARY INVERSE MULTIPLEXING OVER ATM DATA SHEET PMC-2001723 ISSUE 3
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* * * * * *
UTOPIA L2 receive slave can also appear as a single port with the logical port provided as a prepend or in the HEC/UDF field. ATM transmit interface supports 8- and 16-bit UTOPIA L2 and Any-PHY cell interfaces at clock rates up to 52 MHz. Each link configured for cell delineation or each IMA group appears as a PHY port on the Any-PHY and UTOPIA L2 bus. Any-PHY transmit slave appears as an 8-port multi-PHY. The PHY-ID of each cell is identified in the in-band address. UTOPIA L2 transmit slave appears as an 8-port multi-PHY. Seamlessly interconnects to PMC-Sierra's PM7326 S/UNI-APEX ATM/Packet Traffic Manager and Switch and PM7324 S/UNI-ATLAS ATM layer device.
Loopback and Diagnostic Features * * * Supports UTOPIA L2/Any-PHY Loopback (global loopback- where all cells received on the UTOPIA L2 / Any-PHY interface are looped back out) Supports Line Side Loopback (global loopback- where all data received on the line side is looped back out) Supports the capability to trace ICP cells for any group
Software * The S/UNI-IMA device driver, written in ANSI C, provides a well-defined Application Programming Interface (API) for use by application software. Low level utility functions are also provided for diagnostics and debugging purposes. Software wrappers are used for RTOS-related functions making the S/UNI-IMA device driver portable to any Real Time Operating System (RTOS) and hardware environment. The S/UNI-IMA device driver is compatible across the S/UNI-IMA family of devices.
Packaging * Implemented in low power, 0.18 micron, 1.8V CMOS technology with TTL compatible inputs and outputs.
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PRELIMINARY INVERSE MULTIPLEXING OVER ATM DATA SHEET PMC-2001723 ISSUE 3
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* *
Provides a standard 5-pin P1149 JTAG port. 324 ball PBGA, 23mm x 23mm
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3
APPLICATIONS * * * * Digital Subscriber Line Access Multiplexers (DSLAMs) Access Concentrators Integrated Access Devices (IAD) Wireless Base Transceiver Stations
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PRELIMINARY INVERSE MULTIPLEXING OVER ATM DATA SHEET PMC-2001723 ISSUE 3
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4
REFERENCES * * * * * * * AF-PHY-0086.001 "Inverse Multiplexing for ATM (IMA) Specification Version 1.1", March 1999 I.432-1 B-ISDN User Network Interface - Physical Layer specification: General characteristics I.432-3 B-ISDN User Network Interface - Physical Layer specification: 1544 kbps and 2048 kbps operation G.804 "ATM Cell Mapping into Plesiochronous Digital Hierarchy (PDH)" AF-PHY-0016.000 "ATM Forum DS1 Physical Layer Specification" AF-PHY-0064.000 "ATM Forum E1 Physical Interface" ATM Forum, UTOPIA, an ATM-PHY Layer Specification, Level 2, V. 1.0, Foster City, CA USA, June 1995.
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5 5.1
APPLICATION EXAMPLES Multi-Service Access - IADs, Access Concentrators Multi-Service access equipment such as Integrated Access Devices (IADs) and Access Concentrators consolidate voice, data, Internet, and video wide-area network services over ATM unifying the functions of many different types of equipment including CSUs, DSUs, multiplexers and FRADs. Figure 1 illustrates an example of a multi-service access box using IMA over multiple T1/E1 lines for WAN access. Figure 1
AAL1 PM73124 AAL1gator-4
- Multi-Service Access - IADs and Access Concentrators.
UTOPIA L2 / Any-PHY UTOPIA L2
AAL2 PM73140 MECA-4A PM7326 S/UNI-APEX PM7340 S/UNI-IMA-8 Frame Relay over AAL5 PM7366 FREEDM-8 IWF/AAL5 SAR PM7324 S/UNI-ATLAS Clock/Data PM4354 COMETQUAD x 2
On the lineside, the S/UNI-IMA-8 interfaces seamlessly to standard devices such as the PM4354 COMET-QUAD T1/E1 Framer plus LIU. 5.2 Remote DSLAM WAN Uplink IMA is ideally suited for remote DSLAM applications for several reasons. Firstly, remote DSLAMs are physically located at remote sites of which many are served by T1 or E1 lines. Secondly, the benefits of ATM have resulted in its almost exclusive use in DSLAMs. Coupled with ATM, DSLAMs enable service providers to utilize the bandwidth of the T1/E1 infrastructure for delivering integrated services such as high-speed Internet access and real-time voice and video. ATM over T1/E1 is a suitable DSLAM WAN uplink technology and IMA, due to its
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benefits of higher bandwidth, statistical gain and fault tolerance, is even more suitable. Figure 2 illustrates an example of the S/UNI-IMA-8 in a remote DSLAM WAN uplink application. Figure 2 -S/UNI-IMA-8 in a Remote DSLAM WAN Uplink Application.
UTOPIA L2 / Any-PHY UTOPIA L2
PM7326 S/UNI-APEX PM7351 S/UNI-VORTEX PM7324 S/UNI-ATLAS PM7340 S/UNI-IMA-8
Clock/Data PM4354 COMETQUAD x 2
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PRELIMINARY INVERSE MULTIPLEXING OVER ATM DATA SHEET PMC-2001723 ISSUE 3
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6
BLOCK DIAGRAM IMA-8 Block Diagram Figure 3 - S/UNI-IMA-8 Block Diagram
REFCLK
SYSCLK
OE RSTB
D[15:0] A[10:1] ALE WRB RDB CSB INTB
TCK TMS TDI TRSTB TDO
DLL
MicroProcess I/F
JTAG
Tx Slave ATM I/F TCLK TPA TENB TADR[6:0] TCSB TSOP TSX TDAT[15:0] TPRTY
TSCLK[7:0] TSDATA[7:0] CTSCLK
TCAS
TC Layer (TTTC-8)
8-chan x 7 cell FIFO (MCFD)
Tx IMA Processor (TIMA)
8-chan x 3 cell FIFO
AnyPHY/ UTOPIA Tx Slave (TXAPS)
IDCC
Internal Bus
IDCC
Rx IMA Protocol Processor (RIPP) AnyPHY/ UTOPIA Rx Slave (RXAPS)
Rx Slave ATM I/F RCLK RPA RENB RADR[4:0] RCSB RSOP RSX RDAT[15:0] RPRTY
RSCLK[7:0] RSDATA[7:0]
RCAS
TC Layer (RTTC-8)
8-chan x2 cell FIFO
Rx IMA Data Processor (RDAT) Cell Writer Cell Reader
8 chan 4 cell FIFO
Memory Interface (MEMI)
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CBCSB CBRASB CBCASB CBWEB CBA[11:0] CBBS[1:0] CBDQM CBDQ[15:0]
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7
DESCRIPTION The PM7340 S/UNI-IMA-8 is a monolithic integrated circuit that implements the Inverse Multiplexing for ATM (IMA 1.1) protocol with backward compatibility to IMA 1.0 and the Transmission Convergence (TC) layer function. IMA is a protocol designed to combine the transport bandwidth of multiple links into a single logical link. The logical link is called a group. The S/UNI-IMA-8 can support up to 4 independent groups with each group capable of supporting from 1 to 8 links. All links within an IMA group must be at the same nominal rate, however the link rates within a group can be different across groups. The S/UNIIMA-8 can be programmed on a per link basis for cell delination or IMA. The S/UNI-IMA-8 supports 8 T1, E1 or unchannelized links where each link is dynamically configurable to support either IMA 1.1, backward compatible IMA 1.0, ATM over T1/E1, ATM over fractional T1/E1 or ATM HEC cell delination for unchannelized links. Unchannelized links may be used to support applications such as ADSL. The S/UNI-IMA-8 supports a clock and data interface where eight 2-pin serial clock and data interfaces are provided. Each clock and data interface can be configured to simultaneously support combinations of either T1, E1, or unchannelized links. Unchannelized links may be used to support applications such as ADSL. Additionally, for cell delineation only, ATM over fractional T1/E1 is supported by allowing individual DS0 timeslots to be configured as active or inactive. In the transmit direction, the S/UNI-IMA-8 accepts cells from the AnyPHY/UTOPIA interface. As per the IMA specification, the cells, destined for a group, are distributed in a round-robin fashion to the links within the group, adding IMA Control Protocol (ICP) cells, filler cells, and stuff cells as needed. The ICP cells convey state information to the far end and are used to format an IMA Frame. The IMA Frame is used as a mechanism to synchronize the links at the far end. Cell rate decoupling is performed at the IMA sub-layer via filler cells. Filler cells are used instead of physical layer cells for cell rate decoupling, thus a continuous stream of cells is sent to the TC layer. The stuff cells are used to maintain synchronization between links in a group by absorbing the rate differential that exists when links are running at slightly different rates. The data from the IMA sub-layer is passed on to the TC layer. In the TC layer, the HEC is calculated and inserted into the cell headers; optional scrambling of the
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payload is performed. The cell stream is then mapped into a T1 or E1 payload with zeros inserted for the framing and overhead bits or bytes. If using an unchannelized clock and data interface, the data is not mapped into the T1/E1 payload but instead is transmitted one bit for each provided clock pulse. The links are then transmitted via the serial interfaces. The clock is provided from each serial clock pin. An optional common-clock mode is provided to enable all links to run from the same clock. If using an unchannelized clock and data interface, the data is received one bit for each provided clock pulse. On the receive side, data is received from the clock/data interface. The timeslots are mapped to logical channels called links. The TC layer searches for cell delineation as per the procedures outlined in ITU-T Recommendation I.432.1. Once cell delineation is obtained, the payload is optionally descrambled and the cells are passed to the IMA sub-layer. The TC layer provides counts of errored headers as well as OCD and LCD error interrupts. The receive IMA sublayer performs IMA-frame delineation and stuff-cell removal. Based upon the ICP cell information, the S/UNI-IMA-8 determines the differential delay between the links within a group and applies the link and group state machine logic to coordinate the activation and deactivation of groups and links with the far end. As cells are received, they are stored in an external FIFO structure. This structure is based upon the IMA frame boundaries and the IMA frame sequence number. When links or groups are determined to be active by the link and group state machines, the data is played out to the AnyPHY/UTOPIA interface at a constant rate to mimic the existence of a single higher bandwidth physical link. Once a group of links is established, links can be dynamically added or deleted from the group. Under management control, the S/UNI-IMA-8 will perform all necessary steps to add or delete links from previously established groups. In order to aid with diagnostics, a line side loopback and a UTOPIA side loopback are provided. Also, an ICP cell trace feature is provided. When the ICP cell trace has been enabled for a group, the S/UNI-IMA-8 will place those ICP cells where a SCCI field change is detected into a buffer that is accessible to the microprocessor.
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8
PIN DIAGRAM The S/UNI-IMA-8 is packaged in a 324-pin PBGA package that has a body size of 23mm by 23mm and a ball pitch of 1mm. Figure 4 - S/UNI-IMA Preliminary Pinout (Bottom View)
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9
PIN DESCRIPTION Receive Slave ATM Interface (Any-PHY mode) (28 Signals) Pin Name RCLK Type Input Pin No. T21 Function The Receive Clock (RCLK) signal is used to transfer data blocks from the S/UNI-IMA-8 across the receive Any-PHY interface. The RPA, RSOP, RSX, RDAT[15:0], and RPRTY outputs are updated on the rising edge of RCLK. The RENB, RADR[4:0], and RCSB inputs are sampled on the rising edge of RCLK. The RCLK input must cycle at a 52 MHz or lower instantaneous rate. RPA Tristate Output AB22 The Receive Packet Available (RPA) is an active high signal that indicates whether at least one cell is queued for transfer. The S/UNI-IMA-8 device drives the RPA with the cell availability status two RCLK cycles after RADR[4:0] matches the S/UNI IMA's device address. The RPA output is high-impedance at all other times. The RPA output is updated on the rising edge of RCLK. RENB Input W20 The Receive Enable Bar (RENB) is an active low signal used to initiate the transfer of cells from the S/UNI-IMA-8 to an ATM layer component, such as a traffic management device. The RENB input is sampled on the rising edge of RCLK.
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Pin Name RADR[4] RADR[3] RADR[2] RADR[1] RADR[0]
Type Input
Pin No. AA22 Y21 V20 Y22 W22
Function The Receive Address (RADR[4:0]) signals are used to address the S/UNI-IMA-8 device for the purposes of polling and selection for cell transfer. The RADR[4:0] signals are valid only when the RCSB signal is sampled active in the following RCLK cycle. The RADR[4:0] input bus is sampled on the rising edge of RCLK.
RCSB
Input
U21
The Receive Chip Select (RCSB) is an active low signal that is used to select the S/UNI-IMA-8 receive interface. When the RCSB is sampled low, it indicates that the RADR[4:0] sampled at the previous clock is a valid address. If the RCSB is sampled high, the device is not selected and the RADR[4:0] sampled on the previous cycle is not a valid address and is ignored. When sufficient address space is provided by RADR[4:0] for all devices on the bus, this signal may be tied low. The RCSB input is sampled on the rising edge of RCLK.
RSOP
Output
V19
The Receive Start of Packet (RSOP) is an active high signal that marks the start of the cell on the RDAT[15:0] bus. When RSOP is active, the first word of the cell is present on the RDAT[15:0] bus. The RSOP output is updated on the rising edge of RCLK.
RSX
Output
T20
The Receive Start of Transfer (RSX) signal is an active high signal that marks the first cycle of a data block transfer on the RDAT[15:0] bus. When the RSX signal is active, the coinciding data on the RDAT[15:0] bus represents the in-band PHY address. The RSX output is updated on the rising edge of RCLK.
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Pin Name RDAT[15] RDAT[14] RDAT[13] RDAT[12] RDAT[11] RDAT[10] RDAT[9] RDAT[8] RDAT[7] RDAT[6] RDAT[5] RDAT[4] RDAT[3] RDAT[2] RDAT[1] RDAT[0] RPRTY
Type Output
Pin No. U22 T22 U19 R20 R22 T19 R19 P20 P21 P22 P19 N20 N21 N22 N19 M20 M22
Function The Receive Cell Data (RDAT[15:0]) signals carry the ATM cell words that have been read from the S/UNI-IMA-8 internal cell buffers. When this interface is operating in 8-bit mode, the data is carried on RDAT[7:0]. The RDAT[15:0] output bus is updated on the rising edge of RCLK.
Output
The Receive Parity (RPRTY) signal provides the parity (programmable for odd or even parity) of the RDAT[15:0] bus. When the interface is operating in 8-bit mode, the parity is calculated over RDAT[7:0] The RPRTY output is updated on the rising edge of RCLK.
9.1
Receive Slave ATM Interface (UTOPIA L2 mode) (26 Signals) Pin Name RCLK Type Input Pin No. T21 Function The Receive Clock (RCLK) signal is used to transfer data blocks from the S/UNI-IMA-8 across the receive UTOPIA L2 interface. The RCA, RSOC, RDAT[15:0], and RPRTY outputs are updated on the rising edge of RCLK. The RENB and RADR[4:0] inputs are sampled on the rising edge of RCLK. The RCLK input must cycle at a 52 MHz or lower instantaneous rate.
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Pin Name RCA
Type Tristate Output
Pin No. AB22
Function The Receive Cell Available (RCA) is an active high signal that, when polled using the RADR[4:0] signals, indicates if at least one cell is queued for transfer on the selected logical channel FIFO . The S/UNI-IMA-8 device drives RCA with the cell availability status for the polled port one RCLK cycle after a valid RADR[4:0] address is sampled. The RCA output is high-impedance at all other times. The RCA output is updated on the rising edge of RCLK.
RENB
Input
W20
The Receive Enable Bar (RENB) is an active low signal used to initiate the transfer of cells from the S/UNI-IMA-8 to an ATM-layer component, such as a traffic management device. The RENB input is sampled on the rising edge of RCLK.
RADR[4] RADR[3] RADR[2] RADR[1] RADR[0] RSOC
Input
AA22 Y21 V20 Y22 W22 V19
The Receive Address (RADR[4:0]) signals are used to address the S/UNI-IMA-8 device for the purposes of polling and selecting for cell transfer. The RADR[4:0] input bus is sampled on the rising edge of RCLK. The Receive Start of Cell (RSOC) is an active high signal that marks the first word of the cell on the RDAT[15:0] bus. The RSOC output is updated on the rising edge of RCLK.
Output
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Pin Name RDAT[15] RDAT[14] RDAT[13] RDAT[12] RDAT[11] RDAT[10] RDAT[9] RDAT[8] RDAT[7] RDAT[6] RDAT[5] RDAT[4] RDAT[3] RDAT[2] RDAT[1] RDAT[0] RPRTY
Type Output
Pin No. U22 T22 U19 R20 R22 T19 R19 P20 P21 P22 P19 N20 N21 N22 N19 M20 M22
Function The Receive Cell Data (RDAT[15:0]) signals carry the ATM cell words that have been read from the S/UNI-IMA-8 internal cell buffers. When this interface is operating in 8-bit mode, the data is carried on RDAT[7:0]. The RDAT[15:0] output bus is updated on the rising edge of RCLK.
Output
The Receive Parity (RPRTY) signal provides the parity (programmable for odd or even parity) of the RDAT[15:0] bus. When the interface is operating in 8-bit mode, the parity is calculated over RDAT[7:0] The RPRTY output is updated on the rising edge of RCLK.
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9.2
Transmit Slave Interface (ANY-PHY mode) (30 Signals) Pin Name TCLK Type Input Pin No. E19 Function The Transmit Clock (TCLK) signal is used to transfer cells across the ANY-PHY interface to the internal downstream cell buffers. The TPA output is updated on the rising edge of TCLK. The TENB. TSX, TSOP, TDAT[15:0], TPRTY, TADR[6:0], and TCSB inputs are sampled on the rising edge of TCLK. The TCLK input must cycle at a 52 MHz or lower instantaneous rate. TPA Tristate Output L22 The Transmit Packet Available (TPA) is an active high signal that indicates the availability of space in the selected logical channel FIFO when polled using the TADR[6:0] signals. The S/UNI-IMA-8 device drives TPA with the cell availability status of the polled port two TCLK cycles after TADR[6:0] matches the S/UNI IMA's device address. The TPA output is high-impedance at all other times. The TPA output is updated on the rising edge of TCLK. TENB Input L20 The Transmit enable bar (TENB) is an active low signal that is used to indicate cell transfers to the internal cell buffers. The TENB input is sampled on the rising edge of TCLK.
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Pin Name TADR[6] TADR[5] TADR[4] TADR[3] TADR[2] TADR[1] TADR[0] TCSB
Type Input
Pin No. K19 K22 K21 K20 J19 J22 J21 J20
Function The Transmit Address (TADR[6:0]) signals are used to address logical channels for the purpose of polling and device selection. The TADR[6:0] signals are valid only when the TCSB signal is sampled active in the following TCLK cycle. The TADR[6:0] input bus is sampled on the rising edge of TCLK. The Transmit Chip Select (TCSB) is an active low signal that is used to select the S/UNI-IMA-8 transmit interface. When the TCSB is sampled low, it indicates that the TADR[6:0] sampled at the previous clock is a valid address. If the TCSB is sampled high, the device is not selected and the TADR[6:0] sampled on the previous cycle is not a valid address and is ignored. When sufficient address space is provided by TADR[6:0] for all devices on the bus, this signal may be tied low. The TCSB is asserted low one cycle after a valid address is present on the TADR[6:0] signals. The TCSB input is sampled on the rising edge of TCLK.
Input
TSOP
Input
H19
The Transmit Start of Packet (TSOP) is an active high signal that marks the start of the cell on the TDAT[15:0] bus. When TSOP is active, the first word of the cell is present on the TDAT[15:0] bus. The TSOP output is sampled on the rising edge of TCLK.
TSX
Input
H22
The Transmit Start of Transfer (TSX) signal is an active high signal that marks the first cycle of a datablock transfer on the TDAT[15:0] bus. When the TSX signal is active, the coinciding data on the TDAT[15:0] bus represents the in-band PHY address. The TSX output is sampled on the rising edge of RCLK.
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Pin Name TDAT[15] TDAT[14] TDAT[13] TDAT[12] TDAT[11] TDAT[10] TDAT[9] TDAT[8] TDAT[7] TDAT[6] TDAT[5] TDAT[4] TDAT[3] TDAT[2] TDAT[1] TDAT[0] TPRTY
Type Input
Pin No. H21 H20 F19 G22 G21 F22 G20 F21 E22 C20 E21 C22 E20 D21 C21 B22 D20
Function The Transmit Cell Data (TDAT[15:0]) signals carry the ATM cell octets that are transferred to the internal cell buffer. When this interface is operating in 8-bit mode, only TDAT[7:0] is used. The TDAT[15:0] input bus is sampled on the rising edge of TCLK.
Input
The Transmit Parity (TPRTY) signal provides the parity (programmable for odd or even parity) of the TDAT[15:0] bus. The TPRTY signal is considered valid only when valid data and inband address are transferring as indicated by the TENB signal asserted low or the TSX signal asserted high. When this interface is operating in 8-bit mode, this signal provides the parity of TDAT[7:0]. A parity error is indicated by a status bit and a maskable interrupt. The TPRTY input signal is sampled on the rising edge of TCLK.
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INVERSE MULTIPLEXING OVER ATM
9.3
Transmit Slave Interface (UTOPIA L2 mode) (26 Signals) Pin Name TCLK Type Input Pin No. E19 Function The Transmit Clock (TCLK) signal is used to transfer cells across the ANY-PHY interface to the internal downstream cell buffers. The TCA output is updated on the rising edge of TCLK. The TENB, TSOC, TDAT[15:0], TPRTY, TADR[4:0] inputs are sampled on the rising edge of TCLK. The TCLK input must cycle at a 52 MHz or lower instantaneous rate. TCA Tristate Output L22 The Transmit Cell Available (TCA) is an active high signal that indicates the availability of space in the selected logical channel FIFO when polled using the TADR[4:0] signals. The S/UNI-IMA-8 drives TCS with the cell space availability status for the polled port one TCLK cycle after a valid TADR[4:0] address is sampled. The TCA output is high-impedance when not polled. The TCA output is updated on the rising edge of TCLK. TENB Input L20 The Transmit enable bar (TENB) is an active low signal that is used to indicate cell transfers to the internal cell buffers. The TENB input is sampled on the rising edge of TCLK. TADR[4] TADR[3] TADR[2] TADR[1] TADR[0] Input K21 K20 J19 J22 J21 The Transmit Address (TADR[4:0]) signals are used to address logical channels for the purposes of polling and device selection. The TADR[4:0] input bus is sampled on the rising edge of TCLK.
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INVERSE MULTIPLEXING OVER ATM
Pin Name TSOC
Type Input
Pin No. H19
Function The Transmit Start of Cell (TSOC) is an active high signal that marks the first word of the cell on the TDAT[15:0] bus. The TSOC input is sampled on the rising edge of TCLK.
TDAT[15] TDAT[14] TDAT[13] TDAT[12] TDAT[11] TDAT[10] TDAT[9] TDAT[8] TDAT[7] TDAT[6] TDAT[5] TDAT[4] TDAT[3] TDAT[2] TDAT[1] TDAT[0] TPRTY
Input
H21 H20 F19 G22 G21 F22 G20 F21 E22 C20 E21 C22 E20 D21 C21 B22 D20
The Transmit Cell Data (TDAT[15:0]) signals carry the ATM cell octets that are transferred to the internal cell buffer. The TDAT[15:0] signals are considered valid only when the TENB signal is asserted low. When this interface is operating in 8bit mode, only TDAT[7:0] is used. The TDAT[15:0] input bus is sampled on the rising edge of TCLK.
Input
The Transmit Parity (TPRTY) signal provides the parity (programmable for odd or even parity) of the TDAT[15:0] bus. The TPRTY signal is valid only when valid data is transferring as indicated by the TENB signal asserted low. When this interface is operating in 8-bit mode, this signal provides the parity of TDAT[7:0]. A parity error is indicated by a status bit and a maskable interrupt. The TPRTY input signal is sampled on the rising edge of TCLK.
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PM7340 S/UNI-IMA-8
INVERSE MULTIPLEXING OVER ATM
9.4
Microprocessor Interface (31 Signals) Pin Name D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] ALE Type I/O Pin No. B18 B17 D18 C16 A17 B16 C15 D17 A16 B15 A15 B14 A14 D14 C13 B13 A13 D13 C12 B12 D12 A11 B11 D10 A10 B10 C10 Function The Micro Data (D[15:0]) signals provide a data bus to allow the S/UNI-IMA-8 device to interface to an external microprocessor. Both read and write transactions are supported. The microprocessor interface is used to configure and monitor the S/UNIIMA-8 device.
Input
The Micro Address (A[10:1]) signals provide an address bus to allow the S/UNI-IMA-8 device to interface to an external microprocessor. The A[10:1] indicate a word address. The S/UNIIMA-8 microprocessor interface is not byte addressable. The A[10:1] input signals are sampled while the ALE is asserted high. The Address Latch Enable (ALE) is an active high signal that latches the A[10:1] signals during the address phase of a bus transaction. When ALE is set high, the address latches are transparent. When ALE is set low, the address latches hold the address provided on A[10:1]. The ALE input has an internal pull-up resistor.
Input
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INVERSE MULTIPLEXING OVER ATM
Pin Name WRB
Type Input
Pin No. D9
Function The Write Strobe Bar (WRB) is an active low signal that qualifies write accesses to the S/UNI-IMA-8 device. When the CSB is set low, the D[15:0] bus contents are clocked into the addressed register on the rising edge of WRB. The Read Strobe Bar (RDB) is an active low signal that qualifies read accesses to the S/UNI-IMA-8 device. When the CSB is set low, the S/UNI-IMA-8 device drives the D[15:0] bus with the contents of the addressed register on the falling edge of RDB. The Chip Select Bar (CSB) is an active low signal that qualifies read/write accesses to the S/UNI-IMA-8 device. The CSB signal must be set low during read and write accesses. When the CSB is set high, the microprocessor-interface signals are ignored by the S/UNI-IMA-8 device. If the CSB is not required (register accesses are controlled only by WRB and RDB), then it should be connected to an inverted version of the RSTB signal.
RDB
Input
A9
CSB
Input
B9
INTB
OpenDrain Output
C9
The Interrupt Bar (INTB) is an active low signal indicating that an enabled bit in the Master Interrupt Register was set. When INTB is set low, the interrupt is active and enabled. When INTB is tristate, there is no interrupt pending or it is disabled. INTB is an open drain output and should be pulled high externally with a fast resistor.
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PM7340 S/UNI-IMA-8
INVERSE MULTIPLEXING OVER ATM
9.5
SDRAM I/F (35 Signals) Pin Name CBCSB Type Output Pin No. AB6 Function The Cell Buffer SDRAM Chip Select Bar (CBCSB) is an active low signal used to control the SDRAM. CBCSB, CBRASB, CBCASB, and CBWEB define the command being sent to the SDRAM. The CBCSB output is updated on the rising edge of SYSCLK. CBRASB Output AB7 The Cell Buffer SDRAM Row Address Strobe Bar (CBRASB) is an active low signal used to control the SDRAM. CBCSB, CBRASB, CBCASB, and CBWEB define the command being sent to the SDRAM. The CBRASB output is updated on the rising edge of SYSCLK. CBCASB Output W6 The Cell Buffer SDRAM Column Address Strobe Bar (CBCASB) is an active low signal used to control the SDRAM. CBCSB, CBRASB, CBCASB, and CBWEB define the command being sent to the SDRAM. The CBCASB output is updated on the rising edge of SYSCLK. CBWEB Output Y8 The Cell Buffer SDRAM Write Enable Bar (CBWEB) is an active low signal used to control the SDRAM. CBCSB, CBRASB, CBCASB, and CBWEB define the command being sent to the SDRAM. The CBWEB output is updated on the rising edge of SYSCLK.
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Pin Name CBA[11] CBA[10] CBA[9] CBA[8] CBA[7] CBA[6] CBA[5] CBA[4] CBA[3] CBA[2] CBA[1] CBA[0] CBBS[1] CBBS[0]
Type Output
Pin No. AA8 W7 Y9 AA9 AB9 W9 Y10 AA10 AB10 W10 AB11 W11 W12 AA12
Function The Cell Buffer SDRAM Address (CBA[11:0]) signals identify the row address (CBA[11:0]) and column address (CBA[7:0]) for the locations accessed. The CBA[11:0] output is updated on the rising edge of SYSCLK.
Output
The Cell Buffer SDRAM Bank Select (CBBS[1:0]) signals determine which bank of a dual/quad bank Cell Buffer SDRAM chip is active. CBBS is generated along with the row address when CBRASB is asserted low. The CBBS[1:0] outputs are updated on the rising edge of SYSCLK.
CBDQM
Output
Y12
The Cell Buffer SDRAM Input/Output Data Mask (CBDQM) signal is held high until the SDRAM initialization is complete and then set low for normal operation. The CBDQM output is updated on the rising edge of SYSCLK.
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PM7340 S/UNI-IMA-8
INVERSE MULTIPLEXING OVER ATM
Pin Name CBDQ[15] CBDQ[14] CBDQ[13] CBDQ[12] CBDQ[11] CBDQ[10] CBDQ[9] CBDQ[8] CBDQ[7] CBDQ[6] CBDQ[5] CBDQ[4] CBDQ[3] CBDQ[2] CBDQ[1] CBDQ[0]
Type I/O
Pin No. W13 AB13 AA13 Y13 W14 AB14 AA14 W15 AA15 Y15 AB16 AA16 Y16 W18 AA17 AB18
Function The Cell Buffer SDRAM Data (CBDQ[15:0]) signals interface directly with the Cell Buffer SDRAM data ports. The CBDQ[15:0] bi-directional signals are sampled and updated/tristated on the rising edge of SYSCLK.
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PRELIMINARY INVERSE MULTIPLEXING OVER ATM DATA SHEET PMC-2001723 ISSUE 3
PM7340 S/UNI-IMA-8
INVERSE MULTIPLEXING OVER ATM
9.6
Clk/Data (33 signals) Pin Name TSCLK[7] TSCLK[6] TSCLK[5] TSCLK[4] TSCLK[3] TSCLK[2] TSCLK[1] TSCLK[0] Type Input Pin No. F2 D3 G3 G2 G1 F4 H1 H3 Function The Transmit Serial Clock (TSCLK[7:0]) signals contain the transmit clocks for the 8 independently timed links. The TSDATA[7:0] signals are updated on the falling edge of the corresponding TSCLK[7:0] clock. For channelized T1 or E1 links, TSCLK[n] must be gapped during the framing bit (for T1 interfaces) or during time-slot 0 (for E1 interfaces) of the TSDATA[n] stream. The S/UNIIMA-8 uses the gapping information to determine the time-slot alignment in the transmit stream. For unchannelized links, TSCLK[n] must be externally gapped during the bits or time-slots that are not part of the transmission format payload (i.e., not part of the ATM Cell). The TSCLK[7:0] input signal is nominally a 50% duty cycle clock of 1.544 MHz for T1 links and 2.048 MHz for E1 links. The TSCLK[7:0] may operate at higher rates in the unchannelized mode. At higher rates, the amount of lines available is limited. See 12.3.1.2 for more details.
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Pin Name TSDATA[7] TSDATA[6] TSDATA[5] TSDATA[4] TSDATA[3] TSDATA[2] TSDATA[1] TSDATA[0]
Type Output
Pin No. H4 J3 J2 J1 J4 K2 K1 K4
Function The Transmit Serial Data (TSDATA[7:0]) signals contain the transmit data for the 8 independently timed links. For channelized links, TSDATA[n] contains the 24 (T1) or 31 (E1) time-slots that comprise the channelized link. TSCLK[n] must be gapped during the T1 framing bit position or the E1 frame alignment signal (time-slot 0). The S/UNI-IMA-8 uses the location of the gap to determine the channel alignment on TSDATA[n]. For unchannelized links, TSDATA[n] contains the ATM cell data. For certain transmission formats, TSDATA[n] may contain place holder bits or timeslots. TSCLK[n] must be externally gapped during the place holder positions in the TSDATA[n] stream. The TSDATA[7:0] output signals are updated on the falling edge of the corresponding TSCLK[7:0] clock
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Pin Name RSCLK[7] RSCLK[6] RSCLK[5] RSCLK[4] RSCLK[3] RSCLK[2] RSCLK[1] RSCLK[0]
Type Input
Pin No. V1 U2 V4 T3 R1 T4 P3 P2
Function The Receive Serial Clock (RSCLK[7:0]) signals contain the recovered line clock for the 8 independently timed links. The RSDATA[7:0] signals are sampled on the rising edge of the corresponding RSCLK[7:0] clock. For channelized T1 or E1 links, RSCLK[n] must be gapped during the framing bit (for T1 interfaces) or during time-slot 0 (for E1 interfaces) of the RSDATA[n] stream. The S/UNIIMA-8 uses the gapping information to determine the time-slot alignment in the receive stream. RSCLK[7:0] is nominally a 50% duty cycle clock of 1.544 MHz for T1 links and 2.048 MHz for E1 links. For unchannelized links, RSCLK[n] must be externally gapped during the bits or time-slots that are not part of the transmission format payload (i.e., not part of the ATM cell). The RSCLK[7:0] input signal is nominally a 50% duty cycle clock of 1.544 MHz for T1 links and 2.048 MHz for E1 links. The RSCLK[7:0] may operate at higher rates in the unchannelized mode. At higher rates, the amount of lines available is limited See 12.3.1.2 for more details.
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Pin Name RSDATA[7] RSDATA[6] RSDATA[5] RSDATA[4] RSDATA[3] RSDATA[2] RSDATA[1] RSDATA[0]
Type Input
Pin No. V3 Y1 W1 U3 U1 T1 R3 R2
Function The Receive Serial Data (RSDATA[7:0]) signals contain the recovered line data for the 8 independently timed links. For channelized links, RSDATA[n] contains the 24 (T1) or 31 (E1) time-slots that comprise the channelized link. RSCLK[n] must be gapped during the T1 framing bit position or the E1 frame alignment signal (time-slot 0). The S/UNI-IMA-8 uses the location of the gap to determine the channel alignment on RSDATA[n]. For unchannelized links, RSDATA[n] contains the ATM cell data. For certain transmission formats, RSDATA[n] may contain place-holder bits or timeslots. RSCLK[n] must be externally gapped during the place-holder positions in the RSDATA[n] stream. The RSDATA[7:0] input signals are sampled on the rising edge of the corresponding RSCLK[7:0] clock.
CTSCLK
Input
H2
The Common Transmit Serial Clock (CTSCLK) signal contains a common transmit line clock that can be used by all of the 8 serial links instead of the each link's transmit serial line clock (TSCLK[n]). The CTSCLK input signal is nominally a 50% duty cycle clock of 1.544 MHz for T1 links and 2.048 MHz for E1 links.
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9.7
General (5 signals) Pin Name RSTB Type Input Pin No. AA18 Function The Reset Bar (RSTB) is an active low signal that provides an asynchronous S/UNI-IMA-8 reset. RSTB is a Schmitt-triggered input with an internal pull-up resistor. The Output Enable (OE) is an active high signal that allows all of the outputs of the device to operate in their functional state. When this signal is low, all outputs of the S/UNI-IMA-8 go to the high impedance state, with the exception of TDO. The System Clock (SYSCLK) signal is the master clock for the S/UNI-IMA-8 device. The core S/UNIIMA-8 logic (including the SDRAM interface) is timed to this signal. External SDRAM devices share this clock and must have clocks aligned within 0.2ns skew of the clock seen by the S/UNI-IMA-8 device. This clock must be stable prior to deasserting RSTB 0->1. REFCLK Input N2 This clock is required and may operate at frequencies up to 33 MHz. In general, for T1, and E1 rate links, 20 MHz is sufficient. See 12.3.1.3 for details on selecting the proper frequency. No Connect. These balls are not connected to the die.
OE
Input
AB19
SYSCLK
Input
Y7
NC
M2 N1 N3 P4 P1 L4 B2 A1
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Pin Name Reserved
Type
Pin No. C2 B1 D2 E3 C1 D1 E2 F3 L3 L2 M1 M3 N4 W2 Y2 AA1 W3 AB1 Y4 AB2 AA4 AB3 AB4 AA5 Y6 Y3 AB5 AA6 W5 W19 AB20 AA19 AB20 AA19 AA20 Y19 AA21 A20 A19 B8 C8 B7 A6 D6 C7 B6 A5 C6 B5 A4 C5 A2 A3 B3 C4
Function
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INVERSE MULTIPLEXING OVER ATM
9.8
JTAG & Scan Interface (7 Signals) Type Input Pin No. B21 Function The Test Clock (TCK) signal provides timing for test operations that are carried out using the IEEE P1149.1 test access port. The Test Mode Select (TMS) is an active high signal that controls the test operations carried out using the IEEE P1149.1 test access port. The TMS signal has an integral pull-up resistor. The TMS input is sampled on the rising edge of TCK.
Pin Name TCK
TMS
Input
A21
TDI
Input
B20
The Test Data Input (TDI) signal carries test data into the S/UNI-IMA-8 via the IEEE P1149.1 test access port. The TDI signal has an integral pull-up resistor. The TDI input is sampled on the rising edge of TCK.
TDO
Tristate B19
The Test Data Output (TDO) signal carries test data out of the S/UNI-IMA-8 via the IEEE P1149.1 test access port. TDO is a tristate output that is inactive except when the scanning of data is in progress. The TDO output is updated/tristated on the falling edge of TCK.
TRSTB
Input
C18
The Active low Test Reset (TRSTB) is an active low signal that provides an asynchronous S/UNI-IMA-8 test access port reset via the IEEE P1149.1 test access port. TRSTB is a Schmitt-triggered input with an integral pull-up resistor. Note that when not being used, TRSTB must be connected to the RSTB input.
SCAN_MODE Input B
D7
The Active low Scan Mode (SCAN_MODEB) is an active low signal that places the S/UNI-IMA-8 into a manufacturing test mode.
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Pin Name SCANENB
Type Input
Pin No. A8
Function The Active low Scan Enable (SCANENB) is an active low signal that enables the internal scan logic for production testing; it should be held to its inactive high state.
9.9
Power (120 Signals) Pin Name VDDI (1.8 V) Type Power Pin No. E4 U4 AA11 W17 U20 M21 C14 A7 Function The core power pins (VDDI[7:0]) should be connected to a well-decoupled +1.8 V DC supply.
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VSS (VSSI, VSSO, VSSQ)
Ground
A12 AA2 AA3 AA7 AB12 AB15 AB21 AB8 B4 C11 C17 C19 C3 D15 D19 D22 D5 D8 F1 G19 G4 J9 J10 J11 J12 J13 J14 K3 K9 K10 K11 K12 K13 K14 L9 L10 L11 L12 L13 L14 L21 M4 M9 M10 M11 M12 M13 M14 M19 N9 N10 N11 N12 N13 N14 P9 P10 P11 P12 P13 P14 T2 V21 V22 W21 Y11 Y14 Y17
VSS The VSS pins should be connected to GND. VSSO pins are ground pins for ports. VSSQ pins are "quiet" ground pins for ports. VSSI pins are core ground pins. All grounds should be connected together.
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VDD (3.3V)
Power
A18 A22 AB17 D11 D16 D4 E1 F20 L1 L19 R21 R4 V2 W16 W4 W8 Y18 Y20 Y5
VDD (3.3V) The I/O power pins (VDD) should be connected to a well-decoupled +3.3 V DC supply. These pins include the VDDO pins for the switching, as well as the VDDQ for the quiet power pins.
Notes on Pin Description: * * * All S/UNI-IMA-8 I/O present minimum capacitive loading and operate at TTL logic levels and can tolerate 5.0V levels. Inputs RSTB, ALE, TCK, TMS, TDI , TRSTB, TSCLK, CTSCLK, RSCLK, RSDATA, an OE have internal pull-up resistors. Power to the VDD (3.3V) pins should be applied before power to the VDDI (1.8V) pins is applied. Similarly, power to the VDDI (1.8V) pins should be removed before power to the VDD (3.3V) pins is removed.
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10
FUNCTIONAL DESCRIPTION This section describes the function of each entity in the S/UNI-IMA-8 block diagram. Throughout this document the use of the term "transmit" implies data read in from the cell interface and sent out the lineside interface. Conversely, "receive" is used to describe the data path from the lineside interface to the cell interface. The term "virtual PHY" refers to a single flow on the Any-PHY/UTOPIA bus. Each IMA group or a single TC connection is mapped to a virtual PHY. For simplicity, both an IMA group and a TC connection will be referenced as a group. Each IMA group can map data to/from multiple links. Each TC group is mapped to a single link. When supporting fractional T1/E1 via the Clock/Data interface, the timeslots that are chosen to be part of the fractional connection are also referred to as a link.
10.1 Any-PHY/UTOPIA Interface The ATM cell interface is an Any-PHY compliant 8/16 bit slave interface which is compatible with the following options: * * * Any-PHY Slave UTOPIA Level 2, 8-port slave (multi-PHY-mode) UTOPIA Level 2, single port slave (single address mode) for receive side only.
10.1.1 Transmit Any-PHY/UTOPIA Slave (TXAPS) In the transmit direction, each S/UNI-IMA-8 receives cells on the AnyPHY/UTOPIA L2 compatible interface operating at clock rates up to 52 MHz and supporting 16-bit and 8-bit wide data structures. The S/UNI-IMA-8 operates as a bus slave. In the 8- and 16-bit UTOPIA Level 2 Multi-address Slave mode, the transmit interface of the S/UNI-IMA-8 appears as an 8 port multi-PHY. An 11-bit configuration register TCAEN (only 4 bits are used in UL2 mode) controls the response to polling the individual channels within this group of 31 ports. Setting high on TCAEN[0] enables addresses 0 through 7 and TCAEN[3] enables
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addresses 24 through 30. This is typically used to allow more than one slave device to share the Transmit Any-PHY/UTOPIA master bus. In the Any-PHY slave mode, the transmit interface of the S/UNI-IMA-8 appears as a multi-PHY device with 8 ports used for the data path where all ports are identified in the in-band address. The configuration register TCAEN controls the response to polling the individual channels. Setting high on TCAEN[0] enables addresses 0 through 7, and TCAEN[3] enables addressed 24 through 31. This is typically used to allow more than one slave device to share the Transmit AnyPHY/UTOPIA master bus. Conceptually, the Any-PHY protocol can be divided into two processes: polling and cell transfer. Polling in the transmit direction is used by the bus master - typically a traffic buffering and management device - to determine when a buffered data cell can be safely sent to a PHY (or to a virtual PHY in the case of the S/UNI-IMA-8). The S/UNI-IMA-8 provides an independent 3-deep cell buffer FIFO for each virtual PHY. In total, there are 8 FIFOs. This arrangement ensures that there is no headof-line blocking. The traffic manager need only poll those virtual PHYs for which it has cells queued. A cell transfer can be initiated after a polled virtual PHY asserts the TPA output. Each virtual PHY's cell buffer availability status (i.e., the status that will be driven onto the TPA output when the virtual PHY is polled) is deasserted when the first byte of the last cell is written into the buffer. It is re-asserted only when the FIFO can accept another complete cell. In Any-PHY mode, polling is performed using the TADR[10:0] bus in conjunction with the TCSB. Each S/UNI-IMA-8 uses the TADR[2:0] bits to indicate the 8 logical virtual PHYs. The upper bits from the TADR bus, TADR[6:3], are compared to the configured address to select the device. The remaining address bits from the traffic manager are decoded externally and are used to drive the TCSB. The address prepend field in the cell transfer contains the entire 16-bit address. In 8-bit mode, the prepend address is reduced to 8-bits. In Any-PHY mode, the cell transfer is initiated after a successful poll. The virtual PHY address is prepended to the cell, thus performing an inband selection. The S/UNI-IMA-8 monitors the address prepend on the cell transfer to detect its cells. For UTOPIA L2 Mode, Only TADR[4:0] are used for polling and selection. Each FIFO will only assert TCA when polled if it is not in the process of transferring a cell and if there is room in the FIFO for a complete cell. Unlike Any-PHY, in
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UTOPIA L2 Mode the virtual PHY port must first be selected prior to the start of the data transfer. This selection is done using the same address lines that are used for polling in combination with the TENB pin. Data transfers are cell based, that is, an entire cell is transferred from one PHY device before another is selected. Polling occurs concurrently with cell transfers to ensure maximum throughput. Data pausing is not supported in Any-PHY mode. If the TENB is deasserted prior to a complete cell being transferred, the cell transfer error will be triggered. The Transmit Cell Transfer Format is shown in Figure 5 and Figure 6. Word/byte 0 is required for cell transfers to an Any-PHY slave. The address prepend is the S/UNI-IMA-8 virtual PHY ID. The virtual PHY ID can be mapped to a TC link or to an IMA group. Optional prepends are supported, but are ignored by the S/UNIIMA-8. Inclusion of optional words is statically configurable for the interface. The optional words are always ignored. Figure 5 - 16-bit Transmit Cell Transfer Format Bits 15-8
Word 0
Bits 7-0 Address Prepend
(Any-PHY only)
Word 1
Optional Prepend H1 H3 HEC/UDF PAYLOAD1 PAYLOAD3
* * * * * *
(Optional)
Word 2 Word 3 Word 4 Word 5 Word 6
H2 H4 PAYLOAD2 PAYLOAD4
Word 28
PAYLOAD47
PAYLOAD48
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Figure 6
- 8-bit Transmit Cell Transfer Format Bits 7-0
Byte 0
Address Prepend
(Any-PHY only)
Byte 1
Optional Prepend[15:8] Optional Prepend[7:0] H1 H2 H3 H4 HEC PAYLOAD1
* * *
(Optional)
Byte 2
(Optional)
Byte 3 Byte 4 Byte 5 Byte 6 Byte 7*
Byte 8
Byte 55
PAYLOAD48
10.1.2 Receive Any-PHY/UTOPIA Slave (RXAPS) In the receive direction, each S/UNI-IMA-8 transmits cells on an AnyPHY/UTOPIA L2 compatible interface operating at clock rates up to 52 MHz and supporting 16-bit and 8-bit wide data structures. The S/UNI-IMA-8 operates as a bus slave. In the 8 and 16-bit UTOPIA Level 2 Multi-Address Slave mode, the S/UNI-IMA-8 operates as an 8 port multi-PHY with each virtual PHY stored in it's own FIFO. A 4-bit configuration register, RCAEN, controls the response to polling the
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individual channels. Setting RCAEN[0] enables addresses 0 through 7, and RCAEN[3] enables addresses 24 through 30. This is typically used to allow more than one slave device to share the Receive UTOPIA master bus. When polled, the Receive Packet Available (RPA) output indicates whether there is at least one cell available for transfer from the polled link. Upon selection, the interface handles data pausing anywhere in the middle of a cell transfer. In the 8- and 16-bit UTOPIA Level 2 Single Address mode, the S/UNI-IMA-8 operates as a single device with a single cell FIFO, with all cells being identified by their virtual PHY ID (VPHY ID) in an address prepend. The address prepend may be optionally mapped to the HEC/UDF field in order to maintain the standard cell length. When the address presented on the Any-PHY/UTOPIA Interface RADR pins matches a programmable 5-bit configuration register (DEVID), the RXAPS will respond to polls. In all other cases, the output signals are tristated which allows other slave devices to respond. When polled, the RPA output indicates whether there is at least one cell available for transfer from any link. In the 8- and 16-bit Any-PHY Slave mode, the S/UNI-IMA-8 operates as a single device with a single cell FIFO, with all cells being identified by their virtual PHY ID (VPHY ID) in a address prepend. When the address presented on the AnyPHY/UTOPIA Interface RADR pins matches a programmable 5-bit configuration register (DEVID), the RXAPS will respond to polls. In all other cases, the output signals are tristated which allows other slave devices to respond. When polled, the RPA output indicates whether there is at least one cell available for transfer from any link. In Any-PHY mode, data pausing is not supported. In all modes, an optional prepend is allowed on the bus. This prepend will always be set to zero and has no significance to the S/UNI-IMA-8 but is provided for interoperability. To support current and future devices, the interface is configurable as either an Any-PHY or UTOPIA L2 interface. Table 3 summarizes the distinctions between the two protocols. Table 3 UTOPIA L2 and Any-PHY Comparison UTOPIA L2 RDAT[15:0], RPRTY, and RSOP are driven or become high impedance immediately upon sampling RENB low or Any-PHY RDAT[15:0], RPRTY, RSOP and RSX are driven or become high impedance on the RCLK rising edge
Attribute Latency
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high, respectively. The RPA is driven with the cell availability status one CLK cycle after the RADR[4:0] pins match the S/UNI-IMA8's address. A match is defined as either matching the programmed value in single PHY mode or being within the correct range for multi-PHY mode. RSX Undefined. It is low when not high impedance. High coincident with the first word of the cell data structure. Permitted by deasserting RENB high, but the S/UNIIMA's address must be presented on RADR[4:0] the last cycle RENB is high to reselect the same PHY. Not supported. A subsequent cell is output (provided one is available) if RENB is held low beyond the end of a cell.
following the one that samples RENB low or high, respectively. The RPA is driven with the cell availability status two CLK cycles after RADR[4:0] pins match the S/UNI-IMA-8's address.
High coincident with the first word of the cell data structure. High coincident with the first byte of the cell header. Not Permitted.
RSOP
Paused transfers
Autonomous deselection
The outputs become high impedance after the last word of a cell is transferred and until the S/UNI-IMA-8 is reselected.
The cell format for the receive direction is the same as the transmit interface; see Figure 7 and Figure 8 for the formats.
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Figure 7
- 16-bit Receive Cell Transfer Format Bits 15-8 Bits 7-0 Address Prepend
Word 0
(Any-PHY and single channel UL2 only)
Word 1
Optional Prepend H1 H3 HEC/UDF PAYLOAD1 PAYLOAD3
* * * * * *
(Optional)
Word 2 Word 3 Word 4* Word 5 Word 6
H2 H4 PAYLOAD2 PAYLOAD4
Word 28
PAYLOAD47
PAYLOAD48
Note: HEC/UDF may contain the address prepend for Single Channel UL2
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Figure 8
- 8-bit Receive Cell Transfer Format Bits 7-0
Byte 0
Address Prepend
(Any-PHY and single channel UL2 only)
Byte 1
Optional Prepend[15:8] Optional Prepend[7:0] H1 H2 H3 H4 HEC PAYLOAD1
* * *
(Optional)
Byte 2
(Optional)
Byte 3 Byte 4 Byte 5 Byte 6 Byte 7*
Byte 8
Byte 55
PAYLOAD48
Note: HEC field may contain the address prepend for Single Channel UL2 For Any-PHY mode or single-PHY mode, the address prepend field encoding indicates the virtual PHY ID. The virtual PHY ID contains 2 sections, the lower 7 bits indicates the virtual PHY ID, while the upper bits indicate the device address. For UTOPIA multi-PHY mode, the address prepend is not used.
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10.1.3 Summary of Any-PHY/UTOPIA Modes The following table summarizes the available modes of the Any-PHY/UTOPIA Interfaces
Mode Dir & Protocol TX Poll
UL2 Single PHY Not supported
UL2 Multi-PHY PHY Channels: 8 Channel Enable Register: TCAEN(3:0) Channel Address Pins: TADR(2:0) Status Pin: TCA
Any-PHY PHY Channels: 8 Channel Enable Register: TCAEN(6:0) Device ID Register: CFG_ADDR(6:3) Channel Address Pins: TADR(6:0) Address Qualifier Pin: TCSB Status Pin: TCA
TX Select
Not supported
PHY Channels: 8 Channel Enable Register: TCAEN(3:0) Channel Address Pins: TADR(4:0) Select Pin: TENB
PHY Channels: 8 Channel Enable Register: TCAEN(6:0) Device ID Register: CFG_ADDR(15:7) or (7) Channel Address: Prepend bits (6:0) Device Address: Prepend bits (bit 15:7, for 16 bit mode) or (bit 7 for 8-bit mode) Select Pin: TENB, TSX to indicate first byte of transfer.
TX Transfer
Not supported
Cell Size: 8 bit X 53 or 55 bytes Cell Size: 16 bit X 27 or 28 words Enable Pin: TENB Pause in Cell: w/ TENB
Cell Size: 8 bit X 54 or 56 bytes Cell Size: 16 bit X 28 or 29 words Enable Pin: TENB PHY Channels: 1 (in-band addressing is used to identify virtual PHYs)
RX Poll
PHY Channels: 1
PHY Channels: 8
Device ID Register: DEVID(4:0) Device Address Pins: RADR(4:0) Status Pin: RCA RX Select PHY Channels: 1 Device ID Register: DEVID(4:0)
Channel Enable Register: RCAEN(3:0)
Device ID Register: DEVID(4:0)
Channel Address Pins: RADR(4:0) Device Address Pins: RADR(4:0) Status Pin: RCA PHY Channels: 8 Channel Enable Register: RCAEN(3:0) Status Pin: RCA PHY Channels: 1 Device ID Register: DEVID(4:0)
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Device Address Pins: RADR(4:0) Select Pin: RENB RX Transfer bytes Cell Size: 16 bit X 27, 28 or 29 words Enable Pin: RENB
Channel Address Pins: RADR(4:0) Device Address Pins: RADR(4:0) Select Pin: RENB Select Pin: RENB Cell Size: 8 bit X 54 or 56 bytes Cell Size: 16 bit X 28 or 29 words Enable Pin: RENB Channel Address: Prepend
Cell Size: 8 bit X 53, 54, 55 or 56 Cell Size: 8 bit X 53 or 55 bytes Cell Size: 16 bit X 27 or 28 words Enable Pin: RENB
Channel Address: Prepend or UDF Pause in Cell: w/ RENB
10.1.4 ANY-PHY/UTOPIA Loopback For diagnostic purposes, the capability to loopback all Any-PHY/UTOPIA traffic back to the Any-PHY/UTOPIA bus is provided. Cells are taken from the Transmit group FIFOs and placed into the respective Receive Group FIFOs, or to a single FIFO on a space available basis. 10.2 IMA Sub-layer 10.2.1 Overview The IMA protocol provides inverse multiplexing of a single ATM stream over multiple physical links and reassembles the original cell stream at the far-end. The inverse multiplexing is performed on a cell basis; hence, the IMA protocol is described as a cell-based protocol. See Figure 9 below. The protocol is based upon the concept of an IMA frame. An IMA frame is programmable in size and is delineated by an IMA Control Protocol (ICP) Cell. It is recommended that the ICP cells of each link in the IMA group be offset from each other to reduce the notification time of link/group status changes. The transmitter is responsible for aligning the IMA frames on all links within a group, and for ensuring that cells are transmitted continuously by adding filler cells as necessary. To maintain frame alignment in the presence of independently timed line clocks, a cell based stuffing algorithm is utilized. Since the IMA frames are aligned on transmission, this allows the receive end to recover the IMA frames and align them to remove any differential delay between the physical links.
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Figure 9
- Inverse Multiplexing
IMA Group
Physical Link #0
PHY
PHY
IMA Group
Physical Link #1
PHY
Single ATM Cell Stream from ATM Layer
PHY
Original Cell stream passed to ATM Layer
PHY
Physical Link #2
PHY
IMA Virtual LInk
Tx direction cells distributed across links in round robin sequence Rx direction cells recombined into single ATM stream
10.2.2 IDCC scheduler The IMA Data Cell Clock (IDCC) scheduler calculates the IMA Data Cell Rate (IDCR) for each group that is used by both the Receive and the Transmit IMA processors. There is one scheduler for each direction (TXIDCC and RXIDCC), and each scheduler can monitor the rate of up to 8 reference clocks; each scheduler can also generate up to 8 IDCC clocks based upon IDCR. For each group, the reference link can be selected to be one of the 8 monitored links. Each of the monitored links can only be the reference link for one group. IDCR is calculated using the following equation, with Non and M set independently for each IDCR generator. Non is the number of active links, M is the size of the IMA frame, and TRL Cell Rate (TRLCR) is the cell rate of the reference link. IDCR = Non X TRLCR X (M-1/M) X (2048/2049) TRLCR is generated from the byte rate. The byte rate is obtained by monitoring the data transfers on the internal bus in the TC layer. For each IDCR clock tick, a service request is generated and placed into a rate based FIFO. Since there may be many requests generated in a short amount of time and the rate at which each request is generated may be different, a method is required to arbitrate between the requests to prevent blocking of high rate
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requests by large numbers of low rate requests. To achieve this, each request is placed into a priority FIFO. The priority of the request is based upon its rate. There are a total of 5 rate-based FIFOs. When a service request is accepted by the Transmit IMA processor (TIMA) or the Receive IMA Data Processor (RDAT), the next request to be presented is taken from the highest priority FIFO that has an entry. In this manner, the higher rate requests get higher priority than the lower rate requests. Since the S/UNI-IMA-8 can always service all of the requests, this algorithm limits the CDV experienced by any service request to approximately one inter-arrival time of the service request for each group. Rate changes are restricted to IMA frame boundaries. An IMA frame boundary occurs once every (M-1)*N service requests. When a request is received to change the rate(Non), the request is saved until the next IMA frame boundary, at which point it takes effect. By restricting rate changes to frame boundaries, the rate accuracy is preserved preventing FIFO underflows/overflows. Since rate changes are not instantaneous, a vector that represents the active Link IDs (LIDs) in the group is passed with the service request. In this manner, the entity receiving the service requests is informed of the change in rate and of which links should currently be in the round robin for servicing. All IMA-based rate changes are internally managed by the S/UNI-IMA-8; no user interaction is necessary for correct scheduling. The IDCC is also used for scheduling the TC data flow. In this case, the rate generated is simply the cell rate of the TC link and is not modified for IMA ICP cells or stuff cells according to the following equation: IDCR = TRLCR For all TC connections, the IDCC must be configured in TC mode for the physical link. 10.2.3 Transmit IMA Processor (TIMA) The TIMA is responsible for the transmit IMA functions. This consists of distributing the cells arriving from the ATM layer to links in a group and for inserting ICP cells, filler cells, and stuff cells as required by the IMA protocol. Additionally, the TIMA can support cell transmission on connections using only the Transmission Convergence (TC) sublayer without the use of the IMA protocol sublayer.
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10.2.3.1
IMA Frame
The Transmit IMA processor creates the IMA frame by inserting an ICP cell after every (M-1) cells per link. Values of M supported are 32, 64, 128, and 256. The ICP cell is offset within the IMA frame. This offset is programmable on a per-link basis, and the offsets shouldspread throughout the frame. To aviod interaction between groups, the offsets within a group may not be aligned at the same offset. If offsets are aligned at the same offset within a group, the CDV experienced by other groups will be increased. Each frame is identified with an IMA frame sequence number (IFSN); this number is the same for every link in the group that is within the same frame and increments with each frame. The TIMA is responsible for aligning the transmission of the IMA frame on all links within a group. 10.2.3.2 Stuffing Procedure
The TIMA can support both Independent Transmit clock (ITC) and Common Transmit Clock (CTC) modes. The difference between these modes is the stuffing protocol. The method of stuffing is set independently from the clocking mode present in the ICP cell. In CTC mode, a stuff cell is added after 2048 cells on each link. The stuff cell is identical to the ICP cell and is inserted immediately following the ICP cell. The stuff cell events will occur on the same frame on all links; however, the programmed ICP offsets determine at which cell in the frame the stuff event will occur. In ITC mode, a stuff cell is added to the reference link after 2048 cells on the reference link. On all other links in the group, stuff cells are added as necessary to compensate for data rate differences between the link and the reference link of the group. The added stuff cells (or lack of stuff cells) keep the data rate between links equalized. The stuff cell is generated immediately after the ICP cell and both the ICP cell and the stuff cell are identified as stuff cells via the Link Stuff Indication (LSI) field of the ICP cell. In CTC mode, the stuff event is always advertised in the ICP cell of the preceding frame. The stuff event may also be advertised in the 4 preceding frames. It is programmable per group whether the ICP cell is advertised starting 1 frame or 4 frames prior to the occurrence of the stuff event.
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In ITC mode, the stuff event may also be advertised in the ICP cell of the preceding frame or in the 4 preceding frames. If the stuff event needs to be advertised for 4 preceding frames, a DS1/E1 clock tolerance of +/- 50 ppm is required. If a frequency tolerance greater than +/- 50 ppm is required between the independent transmit clocks, the TIMA can provide the single frame advertisement of stuff events. To determine when a stuff cell is needed on ITC mode links (not the TRL), a link stuff detection unit with rate counters is used to track the relative rate of data being read from the link FIFOs within a group to the rate of data being read from the TRL FIFO for the same group. When the relative rate counter indicates that the rate differences have accounted for a slip of a cell, a stuff cell is inserted. 10.2.3.3 Data Flow
The TIMA can support up to 8 groups (IMA group or TC link). Each FIFO on the ATM-layer interface side represents either an IMA group or a TC group. Each group's behavior is controlled by the internal memory tables and records. For IMA groups, the following internal memory structures are used: 1) the Transmit IMA Group Configuration Record for configuring group options and mapping to a port on the ATM interface (VPHY ID) 2) Transmit IMA Group Context Record contains statistics and the current ICP cell image. 3) Transmit LID to the PHYsical Link Mapping Table is used to map individual physical links into a group and assign the LIDs. 4) TIMA Physical Link Context Record contains per-link statistics, and state information. For TC links, only one record is used, the Transmit Physical Link Record, to maintain statistics and to map the physical link to a port on the ATM interface (VPHY ID). The TIMA performs cell transfers from the group FIFOs to the link FIFOs in response to service requests from the TxIDCC. The TxIDCC schedules both IMA groups, as well as low rate TC-only connections. Groups are scheduled according to their rates. Higher-rate groups are prioritized above the lower-rate groups. The TIMA operates at a rate sufficient to ensure the TxIDCC will not suffer request congestion provided the ICP cells are spread throughout the frame
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on IMA groups. If there is no service request pending, the TIMA remains idle. If a group is unused, no cells will be pulled from the respective group FIFO. Therefore, when de-activating groups, ATM cell flow to the S/UNI-IMA-8 should be terminated prior to de-activating the group in order to prevent stale data from being stored in the group FIFO. 10.2.3.3.1 IMA Service
For each IMA group-service request, a cell is transferred from the group FIFO to one of the link FIFOs. If no cell is available from the group FIFO, an IMA filler cell is generated and placed in the link FIFO. The link FIFOs within a group are serviced in a round-robin fashion, with the round-robin order determined by the LID. If the next link in the round robin is due to receive an ICP cell, the ICP cell is generated using the link and group state information from the Transmit IMA Group Context Record, and the LID and LSI from the link. If a stuff event is scheduled, the stuff ICP cell is also inserted. Whenever an ICP cell is inserted, the IMA group servicing proceeds to the next link in the round robin without waiting for another service request. The IMA group service is complete when either: (1) a cell is transferred from the group FIFO or (2) an ATM filler cell is generated. When links are in the process of being added, but are not yet available for carrying data traffic, IMA frames consisting of filler cells and ICP cells are generated. Such links are not scheduled by the TxIDCC scheduler, but will be processed with the currently active links. During group start-up, even with all of the transmit links in the unusable state, the TxIDCC scheduler is started and IMA frames are generated. During group startup (i.e. links are not yet in the active state), a group can be configured such that received via the UTOPIA L2 / Any-PHY bus can be dropped to avoid the accumulation of stale data or to drop stale data in the group FIFO left over from a previous use of the VPHY ID. . During link additions, IMA frames are generated on new links when they are added to the group. 10.2.3.3.2 TC Only Service
For TC-only mode groups, servicing is also initiated by group service requests from the TxIDCC. However, servicing a group FIFO simply entails transferring a cell from the group FIFO to the proper link FIFO. If a cell is not present in the group FIFO, no cells are transferred and the servicing of the request is complete. In TC mode, no other cells are inserted into the data stream by the IMA sub-layer (physical layer idle cells are generated by the physical layer).
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10.2.3.4
Timing Reference Link Maintenance
It is possible to have the timing reference link for an IMA group change from one link to another while the IMA connection is in operation. If an IMA group is operating in CTC mode, the reference link used for the scheduling is simply switched. The next stuff cell insertion still occurs 2049 cells after the previous stuff. If the IMA group is operating in ITC mode and the reference link is switched, the first stuff insertion on the new TRL occurs at approximately the same frame a stuff would have been inserted had it not become the TRL. At the time of the TRL change, the existing accrued rate differential on the new TRL is used to prorate the number of cells out of 2048 until the next TRL stuff. Although the first stuff will occur at approximately the proper number of cells to maintain the correct differential delay, the actual time of the stuff will be dependent on the new TRL rate. Similarly, the first stuff cell insertion on the previous TRL occurs in approximately the same frame a stuff cell would have been inserted had it still been the TRL although the actual frame for stuff insertion will also be dependent on the rate difference with the new TRL. This minimizes any effects on the differential delay for the group as well as reducing any FIFO level changes. All subsequent stuff cell insertions on the TRL then happen after every 2048 cells and all subsequent stuff cell insertions on the former TRL are dependent only on the link's rate difference from the new TRL.
10.2.4 Receive IMA Data Processor (RDAT) The Receive IMA Data Processor (RDAT) performs the IMA data-flow functions in the receive direction including the IMA Frame Synchronization Mechanism (IFSM), storage of data for accommodating differential delay, defect detection, and playout of data in a round robin fashion. One 16 Mbit (1 Mbit x 16) SDRAM, available as a single chip device, is required. Differential-delay tolerance may be configured through registers on a per-group basis to any value up to a maximum of 279 msec for T1 or 226 msec for E1. Buffering is allocated on a per link basis. Each link is allocated 1024 cell buffers.
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10.2.4.1
Writing data to the Delay Compensation Buffers (DCB)
When there is a full cell of data in the RX Link FIFOs, the link requests service. The RDAT arbitrates between links requiring service in a round-robin fashion When a link is chosen for service, if it is not an IMA link, the cells are stored in external memory in a per link FIFO. For IMA links, the IFSM is performed to locate the IMA Frame. Once the IMA frame is located, the RDAT calculates the location to store the cells. The cells are stored in a time-based FIFO structure. The buffer address for a cell is created from the cell number in the IMA frame concatenated with the lower x (depends upon M) bits of the IMA frame sequence number. Each link has it's own reserved FIFO. The cells are stored in this manner such that they are aligned in time in the external memory and the differential-delay removal is simplified. During periods in which the link is in a defect state, incoming cells will be replaced with filler cells prior to being written to the DCB. 10.2.4.1.1 IMA Frame Synchronization Mechanism (IFSM)
For IMA links, the RDAT performs the IFSM. The IFSM is based upon the cell delineation mechanism in I.432. The details of the IFSM can be found in AF-PHY0086.001 "Inverse Multiplexing for ATM (IMA) Specification Version 1.1", March 1999. The state Machine is shown in Figure 10.
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Figure 10
- IFSM State Machine
Valid ICP at unexpected position (with cell by cell hunting)
Missing ICP Cell
Starting State
=consecutive invalid ICP cells
IMA SYNC (frame by frame)
=consecutive errored ICP cells
IMA HUNT (cell by cell)
One invalid or errored/missing ICP cell =consecutive valid ICP cells One valid ICP cells
IMA PRESYNC (frame by frame)
Valid ICP at unexpected position (with cell by cell hunting)
During group start-up, the fields in the ICP cells are validated by the RX IMA Protocol Processor (RIPP) block and the validated information is used to determine whether the ICP cells are valid or not. Validation by the RIPP checks the group fields of the ICP cell to ensure that they match the rest of the group and checks the LID to ensure that it is unique in the group. An ICP cell is invalid if either the IMA OAM Label, the LID, the IMA_ID, M, IFSN or the offset is not the same as the validated values. If the ICP cell cannot be validated by the RIPP (.i.e the IMA_ID is different from the rest of the group or the LID is a duplicate), the IFSM will remain in the starting state. Once the ICP cells are validated by the RIPP, the IFSM will enter the IMA Hunt state. In this state, each cell will be examined to see if it is a valid ICP cell. When a single valid ICP cell has been received, the IFSM will enter the IMA Presync state. While in the Presync state, at each expected ICP location (determined by the ICP offset and the IMA Frame Length), the cell will be examined (frame by frame).
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Once gamma (=)=valid ICP cells have been received, the IFSM will enter the IMA Sync state. If either: (1) an invalid (or errored) ICP cell is received or (2) a valid ICP cell is received in an unexpected location, the IFSM will re-enter the IMA Hunt state. While in the IMA Hunt state, the stuff indicators will be ignored. While in the IMA Sync state, ICP cells are continually examined for each frame. If beta (=)=consecutive ICP cells with HEC, OCD, or CRC-10 errors (errored ICP cells) are received, then the IFSM will reenter the IMA Hunt state. Also, if alpha (=)=consecutive invalid ICP cells are received, the IFSM will reenter the IMA Hunt state. If a cell is received at the expected ICP position without an HEC error or OCD and without the IMA OAM cell header, it is a missing ICP cell, and the IFSM will reenter the IMA Hunt state immediately. Finally, if a valid ICP cell is received at an unexpected position, the IFSM will re-enter the IMA Hunt state. Alpha, Beta, and Gamma are globally programmable for the device. The RDAT keeps working-counts for these parameters for each link. It should be noted that alpha (the count of consecutive invalid ICP cells) will not be reset upon receipt of an errored cell; although beta (the count of consecutive errored ICP cells) will be reset upon receipt of an invalid ICP cell. 10.2.4.1.2 Stuff Events
At this point, the RDAT detects and removes the stuff cells. Stuff cells are identified by the LSI field with the ICP cells. Stuff events consist of two back-toback ICP cells on the same link. One of the ICP cells is considered a stuff cell. Since stuff cells are inserted for the purpose of equalizing the data rate on links with independent clocks, stuff cells are removed. To improve robustness in the presence of errors, the transmitter is required to advertise that a stuff event is going to occur in the ICP cell in the frame preceding the stuff event. The transmitter may also advertise the stuff event for the 4 frames preceding the stuff event. Once a valid non-errored ICP cell has been received with a LSI of 001, 010, 011, or 100, the RDAT will maintain an internal stuff count in link-context memory. This count will be decremented every frame, until the stuff event occurs. The count will be decremented even if an incoming ICP cell is errored or invalid (as shown in Figure 11). An ICP cell received with an invalid stuff sequence (i.e., LSI of 001, when a LSI of 010 was expected) will be declared invalid, and the internal stuff count will be decremented from the previous value (as shown in Figure 12. The internal count is reset to the maximum when the stuff event occurs. A stuff sequence of 111 followed by 000 is not considered an invalid stuff sequence (i.e.,
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the RDAT will always accept immediate notification of a stuff event, to support the case when the 001 stuff cell was errored). Figure 11 - Stuff Event with Errored ICP (Advanced Indication)
Time Stuff event ICP Cell IFSN # i+4 LSI = 111 stuff_cnt =7 ICP Cell IFSN # i+3 LSI = 000 ICP Cell IFSN # i+3 LSI = 000 ICP Cell IFSN # i+2 LSI = 001 stuff_cnt =1 ICP Cell Errored stuff_cnt =2 ICP Cell IFSN # i LSI = 011 stuff_cnt =3
M-1 Filler or ATM Layer Cells
stuff_cnt =0
IFSN: IMA Frame Sequence Number LSI: Link Stuffing Indication
Figure 12
- Invalid Stuff Sequence (Advanced Indication)
Time Stuff event
M-1 Filler or ATM Layer Cells
ICP Cell IFSN # i+4 LSI = 111 stuff_cnt =7
ICP Cell IFSN # i+3 LSI = 000
ICP Cell IFSN # i+3 LSI = 000
ICP Cell IFSN # i+2 LSI = 001 stuff_cnt =1
ICP Cell IFSN #i+1 LSI=001 stuff_cnt =2
ICP Cell IFSN # i LSI = 011 stuff_cnt =3
stuff_cnt =0
IFSN: IMA Frame Sequence Number LSI: Link Stuffing Indication
10.2.4.1.3
IMA Frame Synchronization with Stuff Events
The RDAT will maintain synchronization while receiving stuff events subjected to HEC or CRC errors, as shown in Figure 13. When one of the ICP cells comprising a stuff event is errored or invalid, the other will be used. If both are errored or invalid, then the internally maintained stuff count will be used to identify the stuff event (given that the advanced indicators were correct). All of the cases assume that the IFSM is in the IMA Sync state prior to the window shown, and that the current errored/invalid counts are zero. Cases (1) through (6) require that alpha or beta be programmed to a value greater than one for synchronization to be maintained. Case (7) requires that alpha or beta be programmed to a value greater than two for synchronization to be maintained. Case (7) also requires that advance link stuff indication be given prior to the window shown in order to detect the stuff event.
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Figure 13
- Errored/Invalid ICP Cells in Proximity to a Stuff Event
Time ICP n+1 (1) ICP ICP ICP n ICP
(2)
ICP
ICP
...
ICP
(3)
ICP
ICP
...
ICP
(4)
ICP
ICP
...
ICP
(5)
ICP
ICP
...
ICP
(6)
ICP
ICP
...
ICP
(7)
ICP
ICP
...
ICP
Stuff event
M-1 Filler or ATM Layer Cells
ICP
HEC/CRC Errored or Invalid ICP Cell
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10.2.4.2
Delay Compensation Buffers
Since IMA must re-create the original cell stream in the proper order, delay compensation buffers (DCBs) are used to remove the differential delay between the links in a group. As cells arrive from each link, they are placed in that link's DCB. Links with the least transport delay will have the largest amount of data in the DCB, while links with the largest amount of transport delay will have the least amount of data in the DCB. At group start-up, all the links are compared to determine the link with the largest transport delay and the link with the least transport delay. The difference between these is the differential delay. Data is queued for all links until the corresponding data arrives for the link with the largest transport delay. Figure 14, shows a group with 3 links with a differential delay of 5 cells. Link 0 has the shortest transport delay and link 2 has the longest transport delay. Once the data has arrived for all of the links, it is played out to the ATM layer at the IDCC rate, thus keeping the depths of each DCB at a nominally constant level. (Depths are instantaneously effected by the presence of stuff cells and ICP cells, but these effects are transitory). Figure 14 - Snapshot of DCB Buffers
DCB Link 0 DCB Link 1 DCB Link 2
Write Pointer 0
19 16 13 10 7 Write Pointer 1 11 8 5 2 Write Pointer 2 6 3
Group Read Pointer
4 1
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When a group is already started, IMA supports the addition of links to the group. As illustrated by Figure 14, adding a link with a transport delay that is within the range of the existing links does not present any problems. The DCB for the new link must be aligned with the existing links and added to the round-robin for playout. Adding a link with a smaller transport delay increases the differential delay of the group. This requires that the depth of the DCB buffer be larger than any of the existing links. As long as the differential delay is within acceptable bounds, the new link can be accepted. The DCB for the new link is aligned with the existing links and added to the round-robin for playout. Figure 15 - Snapshot of DCB Buffers after addition of Link with smaller transport delay
DCB Link 0 DCB Link 1 DCB Link 2 DCB Link3
Write Pointer 3 36 Write Pointer 0 32 25 21 17 13 9 Group Read Pointer 5 1 Write Pointer 1 14 10 6 2 Write Pointer 2 7 3 28 24 20 16 12 8 4
Adding a link with a larger transport delay requires the DCB buffer depth to be smaller than the DCB for the link with the largest delay. If the desired DCB depth for the new link is less than 0, this means that the data for the other links has been played out prior to the arrival of data for the new link. This is shown in Figure 16. For the new link to be accepted, delay must be added to all other links in the group. When delay is added to the other links in the group, the playout of
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ATM cells is halted until enough delay is built up. This causes CDV for the group. Once the delay has been added, the DCB for the new link can be aligned with the existing links and added to the round-robin for playout. Figure 17 shows the case after delay was added to the existing links within the group. The adding of delay to a group may be disabled. In this case, the new link would be rejected due to a LODS defect meaning that the DCB could not be aligned with the group. Figure 16 - Snapshot of DCB Buffers when trying to add Link with larger transport delay
DCB Link 0 DCB Link 1 DCB Link 2 DCB Link3
Write Pointer 0
25 21 17 13 9 Write Pointer 1 14 10 6 2 Write Pointer 2 7 3 Write Pointer 3
Group Read Pointer
5 1
-5
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Figure 17
- Snapshot of DCB Buffers after delay adjustment
DCB Link 0 DCB Link 1 DCB Link 2 DCB Link3
Write Pointer 0
33 29 25 21 17 13 9 Write Pointer 1
22 18 14 10 6 2 Write Pointer 2
15 11 7 3
Write Pointer 3 8 4
Group Read Pointer
5 1
When links are deleted from a group, the DCB buffer depths of the remaining links are not effected. As shown in Figure 18, links 2 and 3 have been deleted from the group and the depth of the delay compensation buffers remain unchanged.
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Figure 18
- Snapshot of DCB Buffers after deletion of links from group
DCB Link 0 DCB Link 1 DCB Link 2 DCB Link3
Write Pointer 0
15 14 13 11 9 7 5 3 1 Write Pointer 1 Removed from group Removed from group
12 10 8 6 4 2
Group Read Pointer
10.2.4.3
IMA Link Error Handling
For IMA operation, the RDAT is responsible for detecting Loss of IMA Frame defects (LIF), Idle Cells on IMA Links, Loss of Cell Delineation defects (LCD), and DCB overruns/underruns that contribute to Loss of Delay Synchronization (LODS). This information is forwarded to the RIPP with the ICP messages for processing and reporting. 10.2.4.3.1 IMA Error/Maintenance State Machine (IESM)
A state machine is maintained for the LIF defect detection. This state machine is called the IMA Error/Maintenance State machine [IESM]. The state diagram for the IESM is shown in Figure 19. The RDAT maintains an IESM for each link. The LIF Defect state is the initial state for this process, thus all links will initially come up in the LIF condition.
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Figure 19
- IMA Error/Maintenance State Diagram
Leaving IMA Sync state Persistence of non-IMA Sync (+2) IMA frames
IMA Working State
Entering IMA Sync state
Out of IMA Frame (OIF) Anomaly State
LIF Defect
Persistence of IMA SYNC for at least 2 IMA frames
The IMA Working state enables the RDAT to write user cells to the DCB. If the IFSM leaves the IMA Sync state, the IESM state machine will transition to the OIF Anomaly state, and the OIF anomaly counter will be incremented. In the OIF Anomaly state, incoming user cells are written as filler cells to the DCB, and write pointers are incremented. If the IFSM does not return to the IMA Sync state within gamma + 2 frames, the IESM state will transition to the LIF Defect state. (Gamma is programmable, and is the same gamma used in the IFSM). If the IMA Sync state is entered prior to gamma + 2 frames, the IESM state will transition back to the IMA Working State. This is considered a "fast recovery" from the OIF Anomaly. In the LIF Defect state, incoming user cells are written as filler cells to the DCB, and write pointers are incremented. The LIF-latched status bit will be set in the link-context memory. The IESM state machine will transition to the IMA Working state when IMA Sync has been detected for two consecutive IMA frames. If the IMA Sync state is entered and then exited during LIF, then the OIF anomaly counter will be incremented. When the IESM enters the working state, user cells may be forwarded once again if an overrun (with respect to the configured depth for the link) is not detected. The overrun detection provides the necessary differential-delay checking required after a defect. 10.2.4.3.2 Loss of Cell Delineation Status (LCD)
LCD is detected by the TC layer and the information is passed to the RDAT. When a link is in LCD, a LCD-latched status bit is set in link context memory,
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which is cleared by the ICP cell processing procedure. Cells received while the LCD latched status bit is set will be written to the DCB as filler cells, and the write pointers will be incremented. After an LCD condition is exited, the delay synchronization of the link must be rechecked and resynchronized. An LCD defect will cause the IFSM state machine to go into the hunt state to ensure the delay synchronization is rechecked. The transition of the IFSM into the hunt state will also cause an OIF anomally. 10.2.4.3.3 DCB Overrun Status
When cells are written into the DCB, overruns will be checked by comparing the group read pointer against the link write pointer. If the difference between the pointers exceeds the maximum allowed DCB depth, then an overrun has been detected. For IMA, this will cause the overrun latched status-in-link context to be set. An overrun condition will not cause the IFSM to exit the sync state. All user cells will be dropped while the overrun condition persists. The overrun condition is reset at the reception of an ICP cell with an acceptable delay as long as the link is clear of LIF or OIF. For TC, an interrupt to the processor will be generated and normal operation will resume once the overrun condition has ended. 10.2.4.3.4 DCB Underrun Status
When cells are read from the DCB, underruns will be checked by comparing the group read pointer against the link write pointer. When an underrun is detected, all user cells will be dropped until the underrun condition is cleared. The underrun condition will only be cleared at the reception of an ICP cell, such that the differential delay may be re-checked. An underrun condition will not cause the IFSM to exit the sync state. 10.2.4.3.5 Idle Cells on IMA Links
When Idle cells are detected on an IMA link, they will be reported. Idle cells on IMA links may be present for two reasons. They may have been inserted at the ATM layer of the transmitter as a rudimentary method for traffic management; in which case the IMA layer should treat them as user cells. Otherwise, they may have been inserted at the TC layer to assist with rate matching; this is illegal for
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IMA links. Idle cells will be treated as user cells by the RDAT for IMA processing and will not be dropped at the IMA sub-layer. 10.2.4.4 DCB Playout
The IDCC scheduler provides the rate for data to be played out to the ATM layer for an IMA group. For each cell to be played out, the IDCC generates a service request. Upon the IDCC service request, the RDAT plays out data from the FIFOs in a round-robin fashion. For each service request, the RDAT runs the round robin servicing until it processes either a filler cell or user cell. If ICP cells are encountered, the ICP cell is dropped and the servicing continues until a user or filler cell is found. If a user cell is found, it is transferred from the external memory to the appropriate group FIFO. If a filler cell is found, it is dropped. The RDAT is not sensitive to the alignment of ICP cells within a group. There is no performance degradation even if all of the ICP cells in a group have the same offset. If the device is in Any-PHY mode or UTOPIA L2 Single Port mode, there is only a single FIFO shared among all of the groups. The RDAT ensures that no more than 16 cells are stored in the shared FIFO for a single group. If the S/UNI-IMA-8 is in UTOPIA L2 Multi-port mode, each group has it's own FIFO. If the group FIFO is not emptied in a timely fashion, data is dropped; this is similar to the procedure used by any other PHY level device. The IDCC service request FIFO will always be serviced regardless of the state of the Group FIFO. For multi-port mode, if the respective Group FIFO is full, the cell will be dropped. In Any-PHY mode and UTOPIA L2 Single Port mode, if either the shared FIFO is full or there are already 16 cells for the current group in the FIFO, the cell will be dropped. 10.2.5 Link/Group State Machines The Receive IMA Protocol Processor (RIPP) block is responsible for maintaining and controlling the link and group state machines. The RIPP can accept commands from the management plane to initiate group and link state machine actions. The RIPP then controls the contents of ICP cells generated for the transmit data path, as well as analyzes the link and group states received within the ICP cells. The receive link and group states are utilized to maintain and update the link and group states. The RIPP coordinates group wide state transactions and performs the group wide procedures such as the Synchronized Link activation during Group Start-up Procedure and the Link Addition and Slow
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Recovery (LASR) procedure. When the links change state, the RIPP also coordinates the rate change between the round-robin procedures located in the receive and transmit data paths and their respective rate schedulers. Since failures are based upon the persistence of defects, the defects are detected and passed as interrupts/status to the management plane. The plane management is responsible for the integration of defects into failure conditions and to set the failure conditions in the S/UNI-IMA-8. Table 4 PM command description Description Starts up a group state machine and the link state machines for the links configured in the group. Group and links need to be configured prior to issuing this command. As a result of this command, the transmitter will start to send out IMA frames on the links specified as part of the group, and the receiver will start to look for and analyze ICP cells received on the links within the group. If a sufficient number of links are detected to be active, the group will transition to the operational state and start to transmit and receive ATM traffic. Remove an existing group and all its links immediately. This command will take the group state machine to the "not configured" state and all of the links in the group to the "not in group" state. The transmit links will cease to transmit IMA frames and will commence to transmit physical-layer idle cells until the links are reused. For group deletion without any loss of data, the links may be deleted or inhibited to stop traffic on the group or the group may be inhibited prior to deleting the group.
Command Add_group
Delete_group
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Restart_group
Restart the specified group. When executed, the GSM goes back to "start-up" state and all tx links return to the "unusable" state and the Rx links return to the "unusable" state but report "Not in Group" since the LID is not yet validated. This command is intended to enable the change of parameters during the group start-up phase and to provide a local group reset for other conditions. Set the internal group inhibiting status flag. Once a group is considered inhibited, it will go to BLOCKED state instead of the OPERATIONAL state when sufficient links exist in the group. If the group is already in OPERATIONAL state when the command is issued, the GSM will go to BLOCKED state, and thus block the TX data path. However, the RX data path remains on.
Inhibit_group
Not_inhibit_group
Clear the internal group inhibiting status. If the group is currently in BLOCKED state, the GSM will go to OPERATIONAL state. Start LASR procedure on one or more links. The links involved may either be new links or existing links with a failure/fault/inhibiting condition. If the group configuration is symmetric, links should be added in both the TX and RX direction.
Start_LASR
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Delete_link
Remove one or more links from the group. If the group configuration is symmetric, links should be deleted in both the Tx and RX directions. When a Tx link is deleted, user traffic is no longer sent on the link and it's state is reported as "Not in Group", but IMA frames are still generated. When either a timeout expires or the FE Rx is detected to be no longer active, the deleted links stop generating IMA frames and start generating idle cells until the link is reused. When an Rx link is deleted, it's state is reported as "Not in Group", but traffic is still received and passed to the ATM layer, until the either a timeout expires or FE Tx state is detected to be no longer active. Data received after this point will no longer be forwarded to the ATM layer. The RX link is available for reuse after all the data accumulated in the DCB has been forwarded to the ATM layer. No data will be lost in the link deletion procedure unless the timeout occurs prior to the FE state change detection.
Set_rx_phy_defect
Indicate to S/UNI-IMA-8 that the given link(s) have/have not physical defects (such as LOS/LOF/OOF/AIS) which are not detectable internally. This causes the S/UNI-IMA-8 to start reporting physical layer defects in the RX Defect Indication field in the ICP field for the affected links.
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Unusable_link
Force Links to an unusable state and provide the cause. For Rx Links, if the cause is inhibited, the links are taken through the blocking state to preserve data sent prior the link being inhibited. If the cause is a fault or a failure condition, the link is taken directly to the UNUSABLE state. At this point, data would have already begun to be discarded due to the defects detected on the link. For Tx Links, data will stop being accepted on the Unusable links and IMA frames will be generated consisting of filler cells.
Update_test_ptn
Update the TX test pattern info to be sent in the outgoing ICP cells. This command is used to activate, deactivate, or change the test pattern that is being sent out on the Group.
Update_TX_TRL
Update the transmit TRL. When a TRL is changed, three steps are performed: (1) the TRL sent in the ICP cell is changed;(2) the TRL used for calculating the IDCC is changed, and (3) the TRL used in the stuffing algorithm is changed.
Read_event
Read and clear the latched event status, and read the link/group status of the specified group and all its links. The result read from the internal context memory is stored in Cmd_data00 through Cmd_data1F. Refer to RIPP Command Data Registers for further details.
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Read_delay
Reads a snapshot of the link-defect status and link-delay information for all of the links within the group. The delay information can be used to determine differential delay, the link with the most delay, and any other delay characteristics of the group. The delay information is provided in units of cells. Adjusts the delay of a group by removing the amount of specified delay. While the delay is being adjusted, links cannot be added or recovered for the group.
Adjust_delay
In addition to performing commands from the plane management, the RIPP processes the ICP cells forwarded by the RDAT. When ICP cells arrive from a group, they may be out of order in time due to differential delay between links. The RIPP must examine the ICP cell and determine if it has any new information that needs processing. This can be determined via the IMA frame number and the SSCI field. When processing the ICP cells and the link states, attention must be taken not to violate the group wide procedures. When link or group states are changed, updated ICP cells are sent to the TIMA for transmission. Any state changes are also communicated to the appropriate schedulers and round-robin processors. 10.2.5.1 Group Start-up and Differential Delay
On group start-up, when at least Prx Links obtain IMA frame synchronization, the links will be evaluated. As each link is evaluated, the differential delay of the accepted links is tracked. If a link cannot be accepted because the acceptance of the link would violate the programmed maximum DCB threshold (fastest link minus current data read pointer), the link will remain in the unusable state and begin to report a LODS defect. Accepted links will begin to report a usable state. At this point, as additional links acquire frame sync, they are evaluated and either are accepted or begin to report an LODS defect. When all links have acquired frame sync or the timer has expired, the accepted receive links are reported as active. If at least Prx links have been accepted, the group state machine transitions to operational.
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If sufficient links are not accepted, the group will not become operational. Note that within any collection of links that are targeted to form an IMA group the group may not become operational even though there are combinations of Prx links that meet the programmed maximum DCB threshold. This would occur in situations where the internal algorithm used to determine link order may not select the combination or "tightest" grouping of links that would otherwise meet the programmed maximum DCB threshold. In this case, the relative delays of the links are available to the plane management (.i.e. microprocessor) using the read_delay command. The microprocessor can then analyze this information, remove the offending link or links and restart the group. 10.2.5.2 Link Addition and Differential Delay
Once a group is started, the delay profile for the group is determined. In order to add links, the delay on the new links must be compatible with the existing links in the group and be able to be synchronized with the existing links within the DCB constraints. There are two mechanisms regarding delay that can be used. The first method uses the guardband capability. At group start-up, a guardband is added to the link with the longest transport delay. This guardband results in additional delay to be queued in the DCBs for each link in the group. The guardband allows for links with a longer transport delay to be added in the future without introducing any additional CDV. The second method allows the delay accumulated per link to be increased dynamically. This method will introduce additional delay to all of the links within the group when a link with a larger transport delay is added to the group. The process of adding additional delay to the links within a group will cause additional CDV to be introduced when the playout of data is stopped while the delay is accumulated. The RIPP determines the delay of the links that are being added and performs the appropriate action to either include the link in the group or to reject the link if the link cannot be synchronized within the DCB constraints If a link is rejected due to delay, a LODS defect will be reported on the link. When links are deleted from the group, the delay of the remaining links is not adjusted. See 10.2.4.2 for more details on the management of the DCB buffers.
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10.2.5.3
Removing accumulated delay
In some situations, removal of accumulated delay may be desired. This usually occurs after a group has been operational for a period of time and the link characteristics in terms of transport delay have changed. The adjust_delay command is provided to remove delay from the group. The execution of this command will effect the CDV of the group while the delay is reduced. Any delay adjustment to the group will also effect the CDV of a connection carried on that group. This is additive, if 20 ms of delay is removed from the group, a particular connection within the group will experience an additional 20 ms of CDV. This will generally only be a concern to CBR or VBR-rt traffic flows. This increase in CDV may cause traffic to be policed out or real time applications to experience slips. To minimize the effect on the group traffic rate, while the delay is being reduced, the ATM cells from the group will be transferred to the ATM layer at a rate of (1+1/16)*IDCR versus IDCR. In other words, the group will playout data 6.25% faster to the ATM layer during the process of delay reduction. The amount of time the delay removal takes depends upon the amount of delay to be removed. For example, a group where 200 ms of delay is to be removed takes approximately 3 seconds for the process to complete. While delay adjustments are being made to a group, new links can not be added and links can not be recovered from an error state. The S/UNI-IMA-8 will reject any requests to start a LASR procedure. However, while delay adjustments are in progress, links can be deleted or made unusable. 10.2.5.4 Group Start-up Procedure
When the Add_Group Command is issued, the Group state machine will enter the start-up state and start to send IMA frames on the configured Tx links. 10.2.5.4.1 Start-up State
While in the start-up state, the configured tx link state machines will be reporting the Unusable state and the rx-link state machines will be reporting Not_In_Group. At this point, the S/UNI-IMA-8 will start to monitor the incoming ICP cells. When ICP cells are received with the FE indicating that the Group is in Start-up, the S/UNI-IMA-8 will transition to the Start-up-Ack state if the M value, the Group Symmetry, the OAM Label and IMA_ID (optional) values are acceptable. Otherwise, the S/UNI-IMA-8 will transition into the Config-Aborted State.
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10.2.5.4.2
Config-Aborted State
When entering the Config-Aborted State, a timer is started and an interrupt is generated. The S/UNI-IMA-8 will stay in the config aborted state until either: 1) The management plane restarts the group using the Restart_Group Command. The restart can be done with either the same parameters or with different parameters. 2) The config-abort timeout expires. 10.2.5.4.3 Start-up-Ack State
When entering the Start-up-Ack State, a timer is started. In the Start-up-Ack state, the S/UNI-IMA-8 waits for the FE to report the Start_Up_Ack state. If the timer expires prior to the FE-reporting Start_Up_Ack (or insufficient links, blocked, or operational states), the S/UNI-IMA-8 transitions back into the Start_Up state. Otherwise, when the FE reports Start-up-Ack, the S/UNI-IMA-8 transitions to the Insufficient Links state. 10.2.5.4.4 Insufficient Links
When in the Insufficient Links state, the Start_LASR command should be executed to start the LASR procedure to bring up additional links The LASR procedure starts two timers; one for the Tx links and one for the Rx links. When the LASR procedure is complete (all links become active or timeout), if sufficient links are active, the group state machine transitions into the Operational State unless the Group is Blocked. If sufficient links are not active after the LASR procedure completes, an interrupt is generated. Since links will only transition into the Active state via a LASR procedure, plane management can activate a new LASR procedure with the same set of links and/or with additional links to bring up the group. 10.2.5.4.5 Blocked and Operational States
While in the Blocked and Operational States, the link state machines are monitored to ensure that sufficient links stay active. If insufficient links are
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detected active, the Group state machine will transition into the insufficient links state and will stop accepting data from the ATM layer for transmission. 10.2.5.5 LASR Procedure
Links will only become active as part of the LASR procedure. The add_group command will automatically spawn a LASR procedure. To add links or recover links after group start-up, the Start_LASR command should be used. If an LASR procedure is in progress, additional Start_LASR commands will be rejected. 10.2.5.5.1 TX Links
When the LASR procedure starts, all Tx Links (participating in the LASR) in the unusable state or not_in_group state will immediately transition into the Usable state if they are not faulted or inhibited. (Note that the FE Rx Links may be reporting "Not in Group" at this point since their LIDs have not been validated). Links in other states will remain in the same state. If test patterns are to be transmitted on the links to test them prior to putting them in service, the Tx links should be configured to be brought up with the inhibited state set. This keeps the Tx links in the unusable state until they are released by a new LASR command (the PM_UNUSABLE status can only be cleared by a LASR). Once the Tx Links start to report the Usable state, a programmable timer is started. When either the timer expires or all of the FE Rx links report the active state, the acceptable Tx Links will transition to the Active state. This completes the LASR for the TX links. 10.2.5.5.2 Rx Links
During the LASR procedure, the LIDs for the receive links are validated. Until the LIDS are validated, the RX Links report the "Not in Group" state. As the LIDS are validated, the Rx Links start to report the unusable state. This transition is not synchronized with other links in the group. After all the receive links have their differential delay checked and have no defects (obtained IMA Frame sync) or a programmable timeout occurs, all of the accepted links will transition to the usable state. After the rx links are reported usable, another programmable timeout is started. Once all of the links are reported TX_Usable by the FE or the timeout expires,
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the accepted links will start to report RX_Active. If operating in symmetrical mode, the TE Tx links nmust be in the usable/Active state in order for the accepted links to transition into RX_Active. If some additional links have become usable since the last timeout, they will skip directly from the unusable to the active state. This completes the LASR for the Rx Links. When the LASR for both the RX and TX links is complete, the LASR procedure is complete. If the LASR completes due to a timeout and not all of the links are in the active state, an interrupt will be generated (if enabled) to inform plane management that the links were not brought to the active state. 10.2.5.6 Deactivating Links
Links may be brought down by either the plane management or by the far end. Plane management may declare a fault on a link, inhibit a link, or delete the link. The Far-end state changes may also cause the link to go down. This is the method of coordinating link deactivation between the NE and FE. 10.2.5.6.1 Far End link deactivation
If the FE Tx states transition into an unusable state, the NE Rx states go to the usable state and all data received prior to this point will be played out. If the FE Rx states transition into a not active state, the NE Tx link will transition into the usable state and stop transmitting data on that link. 10.2.5.6.2 Near End (management) link deactivation
If the NE Rx link is removed from the group, the S/UNI-IMA-8 will transition to the deleted state until all previously received data is played out to the ATM layer; at which point, it will deactivate itself and be removed from the round-robin. In absence of defects, the S/UNI-IMA-8 will bring down the link without loss of data. 10.2.5.7 Rate Changes
When the RIPP changes the state of a link to active, it programs the appropriate IDCC scheduler with the new rate. This is done by providing a vector that identifies the active LIDs for the group. This vector is used to determine the
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number of links for the rate calculation and is then passed on to the TIMA or RDAT to indicate the LIDs to include in the round robin. The IDCC will only change its rate at IMA frame boundaries. 10.2.6 Support of IMA Test Pattern Procedure S/UNI-IMA-8 supports the IMA test pattern procedure in both the TX direction (NE initiated) and RX direction (FE initiated). In the TX direction, the S/UNI-IMA-8 updates the TX test control info and TX test pattern field in the outgoing ICP cells, as prompted by the relevant Update_test_ptn command. Meanwhile, the S/UNI-IMA-8 will always compare the RX test pattern field received in the incoming ICP cells with the TX test pattern value being transmitted, and save the result on a per-link basis in the group context memory. In the RX direction, the S/UNI-IMA-8 always analyzes the TX test control info field in the incoming ICP cells. If the test link command field is set to "active", the TX test pattern field in the incoming ICP cells on the selected link will be copied to the RX test pattern field in the outgoing ICP cells. Otherwise the RX test pattern field in the outgoing ICP cells will be filled with "0xFF". 10.2.7 Support of Symmetric/Asymmetric Operation Modes S/UNI-IMA-8 supports all three possible group symmetry modes: symmetric configuration and symmetric operation; symmetric configuration and asymmetric operation; asymmetric configuration and asymmetric operation. For symmetric configuration, the number of TX and RX links in the group must be the same; for asymmetric configuration, that restriction does not apply. The support for asymmetric/symmetric operation modes is part of the S/UNI-IMA functionality.The symmetric operation mode is treated as a special case of the asymmetric operation, where the TX and RX LSM on the same physical link are inter-dependent. 10.2.8 Support of Different IMA Versions It should be noted that the technique used to report RX information over the Link Information fields in the ICP cells when the group is configured in the symmetrical configuration and operation mode differs in the IMA v1.1 implementations and the IMA v1.0 implementations.
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The details of the differences between IMA v1.1 and IMA v1.0 can be found in appendix C of the ATM Forum IMA 1.1 specification. The S/UNI-IMA-8 is primarily designed to be IMA v1.1 compliant. However, it may also be programmed to analyze the incoming ICP cells and generate outgoing ICP cells using IMA v1.0 style, given the group is symmetrically configured. IMA v1.0 is not supported for asymmetrical groups. Support of IMA V1.0 versus IMA v1.1 is selectable on a per-group basis. Since the rx link state is reported on the TX LID byte, the rx_link state is reported as unusable prior to LID validation unlike in IMA 1.1 where it is reported as "Not in Group" prior to LID validation. 10.2.9 SDRAM Interface The S/UNI-IMA-8 uses the external SDRAM to buffer queued cells. The cellbuffer SDRAM interface permits a single device, with 4M addressing capability, for a total of 8 Mbytes of storage. It has a 16-bit wide data bus, with CRC-16 checking applied on a per-cell basis. Each cell takes up 64 bytes of memory. The CRC-16 is applied to words 0 through 30. If an error occurs, an interrupt is sent to the microprocessor, and the cell is sent to the ATM layer anyway. The following diagram shows the cell storage map with the 64-byte memory boundary.
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Figure 20
- Cell Storage Map
Word # 15 Write Pointer + 0 1 2 3 4 5 6 ... ... 28 29 30 31
Bits DCB Status[15:0] DCB Status[31:16]
0
Header1 Header3
Header2 Header4
Reserved STATUS Payload1 Reserved Payload2
Payload45 Payload47
Payload46 Payload48
Reserved CRC-16
The clock source drawn in Figure 21 and Figure 22 must be completely skew aligned between the S/UNI-IMA-8 and the SDRAM clock input pins. The following diagrams illustrate the various configurations supported:
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Figure 21
- 2 MByte
clock source SYSCLK CBCSB CBRASB CBCASB CBWEB CBBS[0] CBA[11:0] CBDQM CBDQ[15:0] 1 CKE CLK Addr/Ctrl 2 x 2k x 256 x 16 DQM DQ[15:0]
Figure 22
- 8 MByte
clock source SYSCLK CBCSB CBRASB CBCASB CBWEB CBBS[1:0] CBA[11:0] CBDQM CBDQ[15:0] 1 CKE CLK Addr/Ctrl 4 x 4k x 256 x 16 DQM DQ[15:0]
There are three processes, all of which are arbitrated by the SDRAM arbiter, that access the cell buffer SDRAM:
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1. The RDAT, which reads and writes cell and status information. The granularity of access by the RDAT is a concatenated 1-cell write, 1-cell read. Either the write or the read may not be performed, depending on the RDATs requirements. 2. The microprocessor interface, which performs diagnostic reading or writing of 64 bytes of data. This data is aligned with the cell data. This access is only allowed when the SDRAM is placed in Diagnostic mode and is provided to enable SDRAM testing. While it is in diagnostic mode, all regular accesses from the RDAT are disabled 3. The refresh controller, which has a programmable refresh rate. The SDRAM interface will perform the initialization sequence for the SDRAM. This sequence is triggered by the SDRAM enable bit in the SDRAM control register. The sequence will program the SDRAM with a CAS latency of 3, sequential access, write burst mode, and a burst length of 8. Applications should ensure that sufficient time is provided between SDRAM power up and when this enable bit is set. 10.3 Link FIFOs In the transmit direction, per link FIFOs exist to provide an elastic store to ensure proper operation. The number of cells in the FIFO at any particular time varies as a function of the CDV introduced by the insertion of stuff cells and ICP cells, the effects of the physical link interface, and the smoothing of data from the ATM layer for group level CDV. During operation, these FIFOs are loaded a cell at a time and emptied in a TDM fashion. The Link FIFOs in the transmit direction are 8 cells deep. In the receive direction, the link FIFOs serve as an interface between the TDM domain and the ATM cell domain. Cells are gathered in the FIFO for each link and then burst out to the external memory by the RDAT. The Link FIFOs in the receive direction are 2 cells deep. A diagnostic loopback capability is provided to loopback data from the receive link FIFOs to the transmit link FIFO; this will loopback all links when enabled.
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10.4
TC Layer
10.4.1 TX TC Layer (TTTC) The TX TC layer (TTTC) performs the TC layer functions. These functions consist of optional HEC generation, optional payload scrambling, and cell-rate decoupling through physical layer (idle) cell insertion. This function removes data byte by byte from the per-link FIFOs as required to provide data to the physical layer function. When the physical layer function needs a byte of data, it will request data from the (TTTC). The TTTC will then read a byte of data from the per-link FIFO. If that byte is the first byte of a cell and the logical channel FIFO is empty, the TTTC will format the next 53 bytes as a physical layer (idle) cell. If the byte is the fifth byte of a cell, the byte is optionally overwritten by the CRC-8 calculation over the previous four bytes for rd 43 that logical channel. The sixth through 53 bytes may be scrambled by a x +1 self-synchronous scrambler. Note: Since the Link FIFOs are cell based, an underrun cannot happen in the middle of a cell. 10.4.2 Rx TC Layer (RTTC) The Rx TC (RTTC) layer implements HCS cell delineation, payload descrambling, idle cell filtering and header error detection to recover valid ATM cells. These functions are performed in accordance with ITU-T Recommendation I.432.1. Cell delineation is the process of framing to ATM cell boundaries using the header check sequence (HCS) field found in the ATM cell header. The HCS is a CRC-8 (x8 + x2 + x + 1) calculation over the first 4 octets of the ATM cell header. In accordance with ITU-T Recommendation I.432.1, the coset polynomial x6 + x4 + x2 + 1 is added (modulo 2) to the received HCS octet before comparison with the calculated result. When performing delineation, correct HCS calculations are assumed to indicate cell boundaries. The cell delineation circuitry performs a sequential bit-by-bit hunt for a correct HCS sequence. This state is referred to as the HUNT state. When a correct HCS is found, a particular cell boundary is assumed and the PRESYNC state is entered. This state verifies that the previously detected HCS pattern was not a false indication. If the HCS pattern was a false indication, then an incorrect HCS should be received within the next DELTA cells and the delineation state machine falls back to the HUNT
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state. If an incorrect HCS is not found in this PRESYNC period, then a transition to the SYNC state is made, cell delineation is declared, and all non-idle cells with a correct HCS are passed on. In the SYNC state, synchronization is not relinquished until ALPHA consecutive incorrect HCS patterns are found. If this happens, a transition is made back to the HUNT state. The state diagram of the cell delineation process is shown in Figure 23. Figure 23 - Cell delineation State Diagram
correct HCS (bit by bit)
HUNT
Incorrect HCS (cell by cell)
PRESYNC
ALPHA consecutive incorrect HCS's (cell by cell)
SYNC
DELTA consecutive correct HCS's (cell by cell)
The values of ALPHA and DELTA determine the robustness of the cell delineation method. ALPHA determines the robustness against false misalignments due to bit errors. DELTA determines the robustness against false delineation in the synchronization process. ALPHA is chosen to be 7 and DELTA is chosen to be 6. The loss of cell delineation (LCD) alarm is declared after a programmable threshold of incorrect cells occurs while in the HUNT state. The threshold is set by the LCD Count Threshold register. The threshold has a default value of 104, which translates to 28 ms at 1.55 Mbps. All idle cells may be filtered out and not passed to the IMA sub-layer. They are identified as cells containing all-zero VPI and VCI fields and a one in the CLP bit. Optionally, unassigned cells (like idle cells except CLP is a zero) may also be filtered. Note that these should not be filtered for IMA links. All cells with an incorrect HCS octet may optionally be droppped. These cells can also be preserved and tagged as errored. Preservation of HEC errored cells is
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required for correct operation of IMA. Failure to perserve the cells will lead to increased numbers of OIF violations and data misordering. Header correction is not implemented. For IMA operation, there are two unique features: the first is optionally passing cells with errored HEC; the second results in passing cells during OCD and LCD. This is to enable the IMA to perform a fast recovery from error conditions. An OCD event will result in a loss of IMA frame sync to ensure differential delay checking is performed. 10.5 Line Side Physical Layer 10.5.1 TX Clock/Data (TCAS) The S/UNI-IMA-8 supports up to eight 2-pin Clock/Data serial interfaces to interface with standard framers. Each link is independent and has its own associated clock. To enable easier support of CTC, a common clock is also supported using the CTSCLK pin. The S/UNI-IMA-8 responds to the active edge of each transmit clock by generating a single bit. When the external framer needs to insert transmission overhead (such as framing bits) into the data stream provided by the S/UNI-IMA-8, the framer is required to gap the transmit clock provided to the S/UNI-IMA-8. This will prevent the S/UNI-IMA-8 from outputting data bits during the overhead bit period(s). The Transmit Channel Assigner block (TCAS) processes up to eight virtual links. Data for all links is sourced from a single byte-serial stream from the TC layer. For each link, the TCAS provides a holding register. The TCAS also performs parallel-to-serial conversion to form a bit-serial stream. When multiple links are in need of data, TCAS requests data from upstream blocks on a fixed priority basis with link TSDATA[0] having the highest priority and link TSDATA[7] the lowest. Links containing a T1 or an E1 stream may be channelized. Data at each timeslot may be assigned either: (1) to be sourced from the virtual link or (2) to be unassigned. This mechanism of assigning timeslots enables support of fractional links. The link clock should only be active during time-slots 1 to 24 of a T1 stream and inactive during the frame bit. Similarly, the clock is only active during timeslots 1 to 31 of an E1 stream and inactive during the framing byte. The first bit of time-slot 1 of a channelized link is identified by noting the absence of the clock and its re-activation. With knowledge of the transmit link and time-slot identity, the TCAS performs a table look-up to identify which timeslots are in use.
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Links may also be unchannelized. In that case, all data bytes on that link belong to the virtual link. The TCAS performs a table look-up to identify the link to which a data byte belongs using only the outgoing link identity, as no time-slots are associated with unchannelized links. The link clock is only active during bit-times containing data to be transmitted; it is inactive during bit-times that are to be ignored by the downstream devices, such as framing and overhead bits. 10.5.2 Rx Clock/Data (RCAS) The S/UNI-IMA-8 provides up to eight 2-pin Clock/Data serial interfaces for interconnecting to T1/E1 framers. Each link is independent and has its own associated clock. For each link, the data is sent through a serial to parallel conversion to form data bytes. The data bytes are multiplexed, in byte serial format, for delivery to the TC layer. In the event where multiple streams have accumulated a byte of data, multiplexing is performed on a fixed priority basis, with link #0 having the highest priority and link #7 the lowest. For the clock and data interface, the framer must gap the clock for all framing bits for T1 and for the framinging byte for E0. Links containing a T1 or an E1 stream may be channelized. For channelized links, the link clock is only active during time-slots 1 to 24 of a T1 stream; it is inactive during the frame bit. Similarly, the clock is only active during time-slots 1 to 31 of an E1 stream and inactive during the FAS and NFAS framing bytes. Each time-slot may be independently configured to be provisioned (contain valid data) or unprovisioned. The RCAS performs a table lookup to assign the provisioned time-slots to a virtual link. After the selected timeslots are grouped into a virtual link, virtual links are referred to as links. This look-up should be used to remove byte 16 of the E1 frame, since byte 16 contains signaling data not ATM data and is also used to implement a fractional T1 or E1. The first bit of time-slot 1 of a channelized link is identified by noting the absence of the clock and its reactivation. Links may also be unchannelized. In this mode, all data is assumed to be valid ATM data. The link clock is only active during bit times containing data to be processed and inactive during bits that are to be ignored by the RCAS, such as framing and overhead bits. The RCAS provides diagnostic line-side loopback that is selectable on a perchannel basis. When a channel is in diagnostic loopback, data on the received links originally destined for that channel is ignored. Transmit data of that channel is substituted in its place.
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10.6 Microprocessor Interface The Microprocessor Interface Block provides the interrupt logic and an interface to normal-mode registers contained within the design blocks. The normal mode registers are required for normal operation. 10.6.1 Mapping and link identification 10.6.1.1 Clock/Data
The links are identified by sequential numbers from 0 to 7. In order to support multiple fractional flows on a single physical link (up to a maximum of eight fractional flows), the remapping feature may be used to split a single channelized link into multiple virtual physical links. The mapped value is refered to as the physical link ID from the perspective of the IMA Layer. 10.6.1.2 IMA
Within the IMA sublayer, mapping is performed between the physical link IDs and the Any-PHY/UTOPIA L2 virtual PHY address. This mapping can be a one-to-one relationship as for TC connections or it may be a many-to-one relationship as for an IMA group. The physical link to Virtual PHY mapping is independent in the RX and TX directions. The selection of the RX VPHY ID in Any-PHY or single port UTOPIA L2 mode is unconstrained as this ID exists only as a prepend. In multiple port UTOPIA L2 mode, the RX VPHY ID must be a unique value between 0 and 3 for each flow. The selection of the TX VPHY ID is limited by the following rules: * All groups must have a unique value between 0 to 3.
Note: The actual address used on the Any-PHY bus to access a particular channel is a combination of the TX VPHY ID (bits 2:0), which TCAEN bit is set(bits 6:3), and the Tx Any-PHY Address Config Reg(bits 15:7).
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10.6.2 Interrupt Driven Error/Status Reporting The interrupt logic has several layers. The top layer of the interrupt logic, the Master Interrupt Register, indicates from which block the interrupt came. Once the block is determined the processor can access the appropriate block to determine the interrupt cause. 10.6.2.1 TC Layer Interrupts
The TC layer sources 4 different interrupts that are reported through a FIFO structure. As each interrupt occurs it is placed into a FIFO along with a Link Identifier to uniquely identify the link. The error conditions reported through this structure include HEC Errors, Loss of Cell Delineation (LCD) state change, Out of Cell Delineation (OCD) state change, and Receive Link FIFO overflow. To determine the actual states of LCD and OCD it is necessary to query the individual link status. If this FIFO overflows, it is necessary to query the status of all links in order to retrieve accurate state information. 10.6.2.2 IMA Interrupts
The IMA sub-layer sources four interrupts: RIPP_INTR, TIMA_INTR, RDAT_INTR, and ICP_CELL_AVL. The RIPP_INTR indicates that either a status change or an error occurred on an IMA group. The RIPP Interrupt status FIFO contains the groups that have enabled conditions active. The RIPP Interrupt status FIFO is managed so that each group will only ever have a single entry in the FIFO. To facilitate interrupt processing, a RIPP command is provided to gather all interrupts and status for a group and all of the links within the group in one snapshot. TIMA_INTR provides information that a link FIFO has overflowed. During normal operations, this will only happen when: (1) the TIMA is misconfigured or (2) the rate difference between the clocks in an IMA group is greater than the maximum tolerance. To determine which link has experienced a problem, the TIMA Link FIFO Overflow Status registers should be read. RDAT_INTR indicates either: (1) that cells were dropped due to AnyPHY/UTOPIA congestion or (2) that TC group cells were dropped due to FIFO overflow. To determine the cause of the interrupt, the RDAT Master Interrupt register should be read.
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ICP_CELL_AVL indicates that an ICP cell is available in the ICP cell buffer. To enable diagnostics, the capability to forward a group's ICP cells to the microprocessor is provided. When a cell is forwarded to the microprocessor, it is placed in the ICP cell buffer and the interrupt is triggered. As new ICP cells arrive, they overwrite the ICP cell buffer unless the buffer is locked for reading. Once the ICP cell buffer is locked, further ICP cells will not be forwarded until the ICP cell buffer is unlocked. This trace can be enabled on a per-group basis. 10.6.2.3 Miscellaneous Interrupts
MISC_INTR indicates that an interrupt condition exists in the Miscellaneous Interrupt register. These bits are read-and-clear and usually indicate that transitory conditions have occurred, such as parity errors, SDRAM CRC errors, interrupt FIFO overflows, and UTOPIA L2 interface errors. 10.6.3 Registers The Register Memory Map in Table 5 shows where the normal mode registers are accessed. The resulting register organization is split into sections: Master configuration registers, TC Layer, Clock/Data Interface and IMA Sublayer registers. On power up, the S/UNI-IMA-8 requires configuration. For proper operation, register configuration is necessary in order to program addresses for the AnyPHY ports, enable the SDRAM, configure the Line interface and chose IMA or TC mode for each link/group. By default, interrupts will not be enabled. The Line-side-access defaults to a disabled state; this results in all line side output pins being tristated. When the line mode is chosen, Clock/Data, the pins will be enabled. Table 5 Address 0x000 - 0x05E 0x000 0x002 0x004 Register Memory Map Register Master Configuration and Interrupts Global Reset Global Configuration JTAG ID (MSB)
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Address 0x006 0x008 0x00A 0x00C 0x00E 0x010 0x012 0x014 0x0160x01E 0x020 0x022 0x024 0x026 0x028 0x02A0x03E 0x040 0x042 0x044 0x046 0x048 0x04A 0x04C 0x04E 0x050
Register JTAG ID (LSB) Master Interrupt Register Miscellaneous Interrupt Register TC Interrupt FIFO Reserved Master Interrupt Enable Register Miscellaneous Interrupt Enable Register TC Interrupt Enable Register Reserved Transmit Any-PHY/UTOPIA Cell Available Enable Receive UTOPIA Cell Available Enable Receive Any-PHY/UTOPIA Config Register (RXAPS_CFG) Transmit Any-PHY/UTOPIA Config Register (TXAPS_CFG) Transmit Any-PHY Address Config Register (TXAPS_ADD_CFG) Reserved SDRAM Configuration SDRAM Diagnostics SDRAM Diag Burst RAM Indirect Access SDRAM Diag Indirect Burst Ram Data LSB SDRAM Diag Indirect Burst Ram Data MSB SDRAM DIAG WRITE CMD 1 SDRAM DIAG WRITE CMD 2 SDRAM DIAG READ CMD 1 SDRAM DIAG READ CMD 2
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Address 0x0520x05E 0x0600x07E 0x060 0x062 0x0640x06E 0x070 0x072 0x074 0x076 0x078 0x07A0x0FE 0x1000x1FE 0x100 0x102 0x104 0x106 0x108 - 0x13E 0x140 - 0x14E 0x150 0x17E 0x180 0x182
Register Reserved TC Layer TTTC Indirect Status TTTC Indirect Link Data Register #1 TTTC Reserved RTTC Indirect Link Status RTTC Indirect Link Data Register #1 RTTC Indirect Link Data Register #2 RTTC Indirect Link Data Register #3 LCD Count Threshold Reserved Clock/Data Interface RCAS Indirect Link and Time-slot Select RCAS Indirect Channel Data RCAS Framing Bit Threshold RCAS Channel Disable RCAS Reserved RCAS Link #0 to Link #7 Configuration TCAS Reserved TCAS Indirect Link and Time-slot Select TCAS Indirect Channel Data
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Address 0x184 0x186 0x188 0x18A - 0x1BE 0x1C0 - 0x1CE 0x1D0 - 0x1FE 0x2000x3FE 0x200 0x202 0x2040x206 0x208 0x20C 0x20E 0x210 0x212 0x214 0x216 0x218 0x21A 0x21C 0x2200x22C 0x22E 0x230
Register TCAS Framing Bit Threshold TCAS Idle Time-slot Fill Data TCAS Channel Disable Register TCAS Reserved TCAS Link #0 to Link #7 Configuration TCAS Reserved IMA Sublayer RIPP Control RIPP Indirect Memory Access Control RIPP Indirect Memory Data Register Array Delay Configuration Register RIPP Timer Tick Configuration Register Group Timeout Register #1 Group Timeout Register #2 Tx Link Timeout Register Rx Link Timeout Register RIPP Interrupt Status Register RIPP Group Interrupt Enable Register RIPP Tx Link Interrupt Enable Register RIPP Rx Link Interrupt Enable Register RIPP Command Register Command Read Data Control Register ICP Cell Forwarding Status Register
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Address 0X232 0x2400x29E 0x2C00x2DE 0x300 0x302 0x304 0x306 0x308 0x30A 0x30C 0x30E 0x310 0x312 0x314 0x316 0x3180x31E 0x320 0x322 0x324 0x326 0x3280x332 0x32A0x33E 0x340
Register ICP Cell Forwarding Control Register RIPP Command Data Register Array Forwarding ICP Cell Buffer RDAT Indirect Memory Command RDAT Indirect Memory Address RDAT Indirect Memory Data LSB RDAT Indirect Memory Data MSB RDAT Configuration Receive ATM Congestion Status Reserved Receive TC Overrun Status RDAT Master interrupt Status Receive ATM Congestion Interrupt Enable Reserved RDAT Master Interrupt Enable Reserved TIMA Indirect Memory Command TIMA Indirect Memory Address TIMA Indirect Memory Data LSB TIMA Indirect Memory Data MSB TX Link FIFO Overflow Status Reserved TXIDCC Indirect Link Access
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Address 0x342 0x3440x34E 0x350 0x352 0x3540x364 0x366 0x3680x3FF
Register TXIDCC Indirect Link Data Register #1 Reserved RXIDCC Indirect Link Access RXIDCC Indirect Link Data Register #1 Reserved DLL Control Status Reserved
For all register accesses, CSB must be low.
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11
NORMAL MODE REGISTER DESCRIPTION Normal mode registers are used to configure and monitor the operation of the S/UNI-IMA-8. Normal mode registers (as opposed to test mode registers) are selected when A[10] is low. Notes on Normal Mode Register Bits:
1. Writing values into unused register bits has no effect. However, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bits must be written with logic zero. Reading back unused bits can produce either a logic one or a logic zero; hence, unused register bits should be masked off by software when read. 2. All configuration bits that can be written into can also be read back. This allows the processor controlling the S/UNI-IMA-8 to determine the programming state of the block. 3. Writeable normal mode register bits are cleared to logic zero upon reset unless otherwise noted. 4. Writing into read-only normal mode register bit locations does not affect S/UNI-IMA-8 operation unless otherwise noted. 5. Certain register bits are reserved. These bits are associated with megacell functions that are unused in this application. To ensure that the S/UNI-IMA-8 operates as intended, reserved-register bits must only be written with logic zero. Similarly, writing to reserved registers should be avoided.
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11.1 Global and Interrupt Registers Register 0x000: Global Reset Bit 15 14 13:7 6:4 3:0 ID[3:0]: The ID bits can be read to provide a binary number indicating the S/UNI-IMA8 feature version. These bits are incremented only if features are added in a revision of the chip. TYPE[2:0]: The TYPE bits can be read to distinguish the S/UNI-IMA-8 from the other members of the S/UNI-IMA-8 family of devices. The S/UNI-IMA-8 is identified by a value of "001". BIST_DONE The BIST_DONE indicates when the internal ram initialization is complete. Once the ram initialization is complete, the rams may be accessed. Prior to BIST_DONE transitioning to a "1", any ram accesses are ignored. RESET: The RESET bit implements a software reset for the entire S/UNI-IMA-8. If the RESET bit is a logic 1, the entire S/UNI-IMA-8 is held in reset except for the microprocessor interface. While in reset, the only register that is accessible is the Global Reset register. This bit is not self-clearing; therefore, a logic 0 must be written to bring the S/UNI-IMA-8 out of reset. Holding the S/UNI-IMA8 in a reset state effectively puts it into a low power, stand-by mode. A hardware reset sets the RESET bit, thus asserting the software reset. RO RO Type R/W RO Function RESET BIST_DONE Unused TYPE[2:0] ID[3:0] Default 1 X 0 000 0
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Register 0x002: Global Configuration Bit 15:8 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W Type Function Unused CHAN_CD MAX_DCB_DEPT H CTSCLK_SEL LINE_EN LINE_LOOP U2U_LOOP LINE_MODE Reserved Default 0 0 0 0 0 0 0 0
LINE_MODE Enables the selected line interface mode. 0) Disabled (All line Interface signals are tristated.) 1) Clock/Data Mode U2U_LOOP When set, all cells received by the Any-PHY/UTOPIA Interface are sent back out to the Any-PHY/UTOPIA (regardless of single- or multi-addressing mode). For proper operation, if the Receive interface is in multi address UTOPIA mode, the Transmit Interface must also be in UTOPIA Mode. 0) Any-PHY/UTOPIA in normal mode 1) Any-PHY/UTOPIA in remote loopback mode LINE_LOOP When set, all cells received by the Clock/Data interface are sent back out to the Clock/Data interface 0) Line Side in normal mode 1) Line Side remote loopback mode
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LINE_EN Indicates when the LINE_MODE has been set-up and enables the line side traffic flow. CTSCLK_SEL When set and LINE_MODE="10", this selects the CTS_CLK pin to be used as the clock for all Transmit Serial Line Clocks. MAX_DCB_DEPTH: This indicates the number of cells that can be stored for a single link in the external SDRAM. This determines the number of bits the RDAT will use for the read and write pointers. To ensure correct operation, the user must ensure that the proper amount of SDRAM is available. See section 12.6.2 for details. 0) 256 cells per link 1) 1024 cells per link CHAN_CD: This indicates that the channelized cell delineation may be used. Channelized cell delineation results in faster cell delineation since an octet by octet search is performed instead of a bit by bit search. This option may only be used when operating with the clk/data interface in channelized mode. If any links are operating in unchannelized mode, this bit may not be set. 0) Use bit by bit search for cell delineation. (Safe mode) 1) Use octet search for cell delineation (only should be set if operating with channelized line interface for all links
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Register 0x004: JTAG ID (MSB) Bit 15:0 Type RO Function JTAGID(31:16) Default 0x0734
JTAGID[31:16]: The JTAG ID register (JTAGID[31:16]) of the S/UNI-IMA-8 device. The JTAG ID is the same as the one read by the JTAG port. Register 0x006: JTAG ID (LSB) Bit 15:0 Type RO Function JTAGID(15:0) Default 0x00CD
JTAGID[15:0]: The JTAG ID register (JTAGID[15:0]) of the S/UNI-IMA-8 device. The JTAG ID is the same as the one read by the JTAG port.
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11.2 Master Interrupt Interface Register 0x008: Master Interrupt Register Bit 15:9 8 7 6:4 3 2 1 0 Type RO RO RO RO RO RO RO RO Function Unused TC_INTR MISC_INT Reserved ICP_CELL_AVL RDAT_INTR TIMA_INTR RIPP_INTR Default 0 0 0 0 0 0 0 0
This register is the top of the Interrupt Tree. It indicates which lower level interrupt registers have interrupts pending. Note that the respective bits will remain set as long as the underlying condition remains active. RIPP_INTR When set, there is an interrupt pending from the RIPP block. Read the RIPP_INTR_FIFO located in Register 0x216 to determine the group which caused the interrupt. This bit indicates current status and will clear only when RIPP_INTR_FIFO is empty. On read: 0) No interrupt pending from the RIPP block. 1) Interrupt pending from the RIPP block. TIMA_INTR When set, there is an interrupt pending from the TIMA block. Read the TIMA_OVERFLOW_REG located in register 0x328 to determine the link which caused of the interrupt. This bit indicates current status and will clear only when no interrupt conditions remain in TIMA_OVERFLOW_REG. On read: 0) No interrupt pending from the TIMA block. 1) Interrupt pending from the TIMA block.
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RDAT_INTR When set, there is an interrupt pending from the RDAT block. Read the RDAT_INTR_STATUS_REG located in register 0x310 to determine the cause of the interrupt. This bit indicates current status and will clear only when no interrupt conditions remain in RDAT_INTR_STATUS_REG. On read: 0) No interrupt pending from the RDAT block. 1) Interrupt pending from the RDAT block. ICP_CELL_AVL When set, it indicates that a new ICP Cell is available in the ICP cell buffer. The ICP cell buffer can be used to extract ICP cells for a group. This bit is cleared when register 0x230 ICP Cell Forwarding Status is read. 0) No ICP cell is available. 1) An ICP cell is available in the ICP buffer. MISC_INTR When set, it indicates that an interrupt is pending in the Miscellaneous Interrupt Register located in register 0x00A. This bit indicates current status, and will clear only when no interrupt conditions exist in the Miscellaneous Interrupt register. On read: 0) No Miscellaneous interrupt pending 1) Miscellaneous interrupt pending TC_INTR When set, indicates that a TC layer is pending in the TC_INTR_FIFO. This bit indicates current status and will clear only when the TC_INTR_FIFO is empty. 0) No TC Interrupts in the TC_INTR FIFO. 1) TC Interrupts are present in the TC_INTR_FIFO.
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Register 0x00A: Miscellaneous Interrupt Register Bit 15:5 4 3 2 1 0 Type RO RO RO RO RO RO Function Reserved Default 0
TC_INTR_FOVR_ER 0 R SDRAM_CRC_ERR 0 TX_UTOP_CELLXFE 0 RR TX_UTOP_PAR_ER R RX_UTOP_XFR_ER R 0 0
This register collects the miscellaneous interrupts. These interrupt bits are cleared on read. If any bit in this register is set and is enabled, the MISC_INT bit will be set in the Master Interrupt register. RX_UTOP_XFR_ERR When set, it indicates that the Receive Any-PHY/UTOPIA Interface was requested to send a cell when it did not have one available. This condition is a protocol error in the Receive Any-PHY/UTOPIA bus. This bit is cleared on read. 0) No protocol error occurred. 1) The Rx Any-PHY/UTOPIA interface was requested to send a cell when a cell was not available. TX_UTOP_PAR_ERR When set, it indicates that the Transmit ANY-PHY/UTOPIA Interface experienced a parity error. This bit is cleared on read. 0) No parity error occurred on the TX ANY-PHY/UTOPIA interface. 1) A parity error occurred on the TX ANY-PHY/UTOPIA interface. TX_UTOP_CELLXFERR When set, it indicates that the Transmit ANY-PHY/UTOPIA Interface experienced an unexpected start of cell in the middle of a cell transfer. This bit is cleared on read.
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0) No cell transfer error occurred on the TX ANY-PHY/UTOPIA interface. 1) A cell transfer error occurred on the TX ANY-PHY/UTOPIA interface. SDRAM_CRC_ERR When set, it indicates that a SDRAM CRC Error occurred when a cell buffer was read from SDRAM. This bit is cleared on read. 0) No SDRAM CRC error occurred. 1) SDRAM CRC error occurred. TC_INTR_FOVR_ERR When set, it indicates that the TC Interrupt FIFO overflowed and status reporting information was lost. To determine the status of the physical Links, the physical-link status for each link must be polled. This bit is cleared on read. 0) The TC Interrupt FIFO has not overflowed. 1) The TC Interrupt FIOF has overflowed.
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Register 0x00C: TC Interrupt FIFO Bit 15 14 13:11 10:4 3 2 1 0 Type RO RO RO RO RO RO RO RO Function FIFO_BUSY FIFO_NOT_EMPTY Unused LINK_ID HCS_ERR LCD_ERR FOVR_ERR OOCD_ERR Default 0 0 0 0 0 0 0 0
OOCD_ERR When set, it indicates that an OCD error occurred on the link indicated by Link ID. This bit is valid only when FIFO_NOT_EMPTY is set and FIFO_BUSY is not set. 0) No OCDE error occurred on the Link identified by LINK ID. 1) OCDE error occurred on the link identified by LINK ID. FOVR_ERR When set, it indicates that a FIFO Overflow Error occurred on the link indicated by Link ID. This bit is valid only when FIFO_NOT_EMPTY is set and FIFO_BUSY is not set. 0) No FOVRE error occurred on the Link identified by LINK ID. 1) FORVE error occurred on the Link identified by LINK ID. LCD_ERR When set, it indicates that a Loss of Cell Delineation Error occurred on the Link identified by LINK ID. This bit is valid only when FIFO_NOT_EMPTY is set and FIFO_BUSY is not set. 0) No LCDE error occurred on the Link identified by LINK ID. 1) LCDE error occurred on the Link identified by LINK ID.
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HCS_ERR When set, it indicates that a Header Check Sequence Error occurred on the Link identified by LINK ID. This bit is valid only when FIFO_NOT_EMPTY is set and FIFO_BUSY is not set. 0) No HCSE error occurred on the Link identified by LINK ID. 1) HCSE error occurred on the Link identified by LINK ID. LINK_ID[6:0] Indicates the Physical-Link number associated with the error. Valid values range from 0 to 7. This field is valid only when FIFO_NOT_EMPTY is set and FIFO_BUSY is not set. FIFO_NOT_EMPTY Indicates that the FIFO is not empty and that the data read is valid. This bit is valid only when FIFO_BUSY is not set. 0) FIFO empty, data is not valid 1) FIFO not empty, data is valid. FIFO_BUSY Indicates that the FIFO is in the process of retrieving the next entry. The Busy bit will generally be cleared within 4 sysclk cycles from the previous read of this field. While this bit is set, the other contents of this register are invalid.
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Register 0x010: Master Interrupt Enable Register Bit 15:5 8 7 6:4 3 2 1 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function Reserved TC_INTR_EN MISC_INTR_EN Reserved ICP_CELL_AVL_EN RDAT_INTR_EN TIMA_INTR_EN RIPP_INTR_EN Default 0 0 0 0 0 0 0 0
The above enable-bits control the corresponding interrupt bits in the Master Interrupt Register. When an enable-bit is set to a logic 1, the corresponding error event will cause INTB to go active.
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Register 0x012: Miscellaneous Interrupt Enable Register Bit 15:5 4 3 2 1 0 Type RO R/W R/W R/W R/W R/W Function Unused TC_INTR_FOVR_ER R_EN SDRAM_CRC_ERR_ EN TX_UTOP_CELLXFE RR_EN TX_UTOP_PAR_ERR EN Default 0 0 0 0 0
RX_UTOP_XFR_ERR 0 _EN
The above enable-bits control the corresponding interrupt bits in the Miscellaneous Interrupt register. When an enable-bit is set to a logic 1, the corresponding error event will cause the MISC_INT bit to be set in the Master Interrupt Register.
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Register 0x014: TC Interrupt Enable Register Bit 15:4 3 2 1 0 Type RO R/W R/W R/W R\W Function Unused HCS_ERR_EN LCD_ERR_EN FOVR_ERR_EN OOCD_ERR_EN Default 0 0 0 0 0
The above enable-bits provide a global enable for the corresponding interrupt bits in the TC Interrupt FIFO. If an enable-bit is not set, the corresponding error event will not cause an entry to be written into the TC_INTR FIFO. When an enable-bit is set to a logic 1, the corresponding error event, if enabled for the link, will cause an entry to be written into the TC INTR FIFO.
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11.3 UTOPIA Interface Registers These registers control the configuration of the UTOPIA interface. Register 0x020: Transmit Any-PHY/UTOPIA Cell Available Enable Bit 15:11 10:0 Type R R/W Function Unused TCAEN[10:0] Default 0 0
TCAEN[3:0]: The TCAEN[10:0] bits select which group of 8 addresses the device responds to on the Any-PHY/UTOPIA Transmit port. The TCAEN[10:0] bits are used to enable an address range. Only one bit should be set to enable a range of 8addresses. For example, setting TCAEN[0] enables addresses 0 through 7, setting TCAEN[3] enables addresses 24 through 31 and setting TCAEN[10] enables address 80 through 87. Addresses 88 through 127 are not supported on the Any-PHY bus. If a disabled PHY address is polled, TCA remains high impedance. Similarly, PHY selection is ignored and no cell is transferred to the S/UNI-IMA-8 when a disabled PHY is addressed. This is typically used to allow more than one slave device to share the Transmit UTOPIA bus or to preserve addresses on the Any-PHY bus. Disabling all traffic to the AnyPHY/UTOPIA input port is achieved by setting all TCAEN[10:0] bits to logic 0.
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Register 0x022: Receive UTOPIA Cell Available Enable Bit 15:4 3:0 R/W Type Function Unused RCAEN[3:0] Default 0 0
RCAEN[3:0]: The RCAEN[3:0] is used to select which group of 8 addresses the S/UNI-IMA8 responds to. Only one bit should be set. RCAEN[0] corresponds to the address range of 0 to 7 and RCAEN[3] corresponds to the address range of 24 to 30 (Since UTOPIA only supports 31 phys, if the highest range is chosen, the S/UNI-IMA-8 will only support 7 ports.) If a disabled PHY address is polled, RCA remains high impedance. Similarly, PHY selection is ignored and no cell is transferred to the S/UNI-IMA-8 when a disabled PHY is addressed. This is typically used to allow more than one slave device to share the Receive UTOPIA bus. Disabling all traffic to the UTOPIA input port while in Multi-PHY mode is achieved by setting all RCAEN[3:0] bits to logic 0. This field is ignored when in Any-PHY or Single Port UTOPIA mode.
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Register 0x024: Receive Any-PHY/UTOPIA Config Reg (RXAPS_CFG) Bit 15 14:13 12:8 7:6 5 4 3 2 1 0 Type R/W R R/W R R/W R/W R/W R/W R/W R/W Function RA_ENABLE Unused RA_DEVID[4:0] Unused RA_HECUDF RA_PREPEND RA_16_BIT_MOD E RA_EVEN_PAR RA_UTOP_MOD E Default 0 0 0 0 0 0 0 0 0
RA_ANY-PHY_EN 0
This register controls the receive side configuration of the Any-PHY/UTOPIA Interface RA_UTOP_MODE Selects the operating mode for the receive-side interface. This bit is ignored when ANY-PHY_EN is set: 0) UTOPIA-2 Single Address Slave with address prepend. 1) UTOPIA-2 Multi-Address Slave. RA_ANY-PHY_EN Enables Any-PHY mode for receive side interface. 0) UTOPIA mode. (Use RA_UTOP_MODE for UTOPIA type). 1) Any-PHY mode. RA_EVEN_PAR Determines the generated parity across data bytes/words sourced by the receive interface. 0) Odd parity. 1) Even parity.
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RA_16_BIT_MODE When set, the Any-PHY/UTOPIA receive side interface operates in 16-bit mode. 0) 8-bit mode. 1) 16-bit mode. RA_PREPEND When set, a single 2-byte prepend is added on the Any-PHY/UTOPIA bus. This prepend is always zero. 0) No additional prepend 1) Optional 2-byte prepend is included in cell length. RA_HECUDF This bit is only valid in Single Address UTOPIA Mode. 0) Place the virtual PHY ID in a prepend. 1) Place the virtual PHY ID in the HECUDF. RA_DEVID[4:0] This field provide the device ID that is used for polling and selection in the Any-PHY mode or in the Single Address UTOPIA Mode. When the address presented on the Any-PHY/UTOPIA RADR Interface pins matches this address, the S/UNI-IMA-8 will respond to polls. The S/UNI-IMA-8 is selected by placing when the address on RADR at the last cycle that RENB is high matches the RA_DEVID. RA_ENABLE Enables the Receive Any-PHY/UTOPIA interface. Prior to this bit being set, all outputs are tristated and all inputs are ignored on the Interface.
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Register 0x026: Transmit Any-PHY/UTOPIA Config Reg (TXAPS_CFG) Bit 15 14:5 4 3 2 1 0 Type R/W R R/W R/W R/W R/W R/W Function TA_ENABLE Unused TA_PREPEND TA_16_BIT_MOD E TA_EVEN_PAR TA_ANY-PHY_EN Unused Default 0 0 0 0 0 0 0
This register controls the transmit-side configuration of the Any-PHY/UTOPIA Interface TA_ANY-PHY_EN Enables Any-PHY mode for the transmit side interface: 0) UTOPIA-2 Multi-Address Slave 1) Any-PHY mode. TA_EVEN_PAR Determines the generated parity across data bytes/words received by the Any-PHY/UTOPIA transmit Interface. 0) Odd parity 1) Even parity. TA_16_BIT_MODE When set, the TX Any-PHY/UTOPIA interface operates in 16-bit mode. 0) 8-bit mode 1) 16-bit mode TA_PREPEND: When set, a single 2-byte prepend is expected on the Any-PHY/UTOPIA transmit interface. This prepend is indepent of the address prepend used for Any-PHY mode. The prepend is ignored, but the capability is provided to enhance interoperability.
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0) No additional prepend 1) Optional 2-byte prepend is included in cell length. TA_ENABLE Enables the Transmit Any-PHY/UTOPIA interface. Prior to this bit being set, all outputs are tristated and all inputs are ignored on the Interface.
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Register 0x028: Transmit Any-PHY Address Config Register (TXAPS_ADD_CFG) Bit 15:7 6:0 Type R/W R/W Function Default
CFG_ADDR_MSB 0 Unused 0
CFG_ADDR_MSB(15:7) These bits contain the configured slave address used for Any-PHY operation in the transmit direction. Depending on the mode of the Any-PHY/UTOPIA interface different bits of this field are used
NOTES: 1) In Any-PHY 16-bit mode, the upper 9 bits of the prepended address are compared with CFG_ADDR[15:7]. The bottom seven bits are compared with the address range selected in the TCAEN register to determine if the device is selected. 2) In Any-PHY 8-bit mode, just CFG_ADDR[7] is used to select the device. 3) In UTOPIA Mode, this register is not used. To disable UTOPIA transmit ports, the Any-PHY/UTOPIA Transmit Cell-available register is provided.
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11.4 SDRAM Configuration and Diagnostic access Register 0x040: SDRAM Configuration Bit 15:12 11:1 0 R/W R/W Type Function Unused REF_RATE [10:0] SDRAM_EN Default 0 0 0
This register configures and enables the SDRAM interface. SDRAM_EN The SDRAM_EN enables the SDRAM interface. A transition from 0 to 1 starts the SDRAM initialization procedure; this procedure takes 70 SYSCLK cycles. Note that no other SDRAM accesses are allowed during this period. This SDRAM_EN is provided to ensure that the power-up of the SDRAM is completed before the initialization sequence is applied. The power-up time is controlled by SDRAM_EN. Typically, this must be at least 200 us. When SDRAM_EN = `0', no SDRAM accesses will take place and the chip will not operate properly. 0) SDRAM accesses are disabled 1) SDRAM accesses are enabled REF_RATE[10:0] Defines the SYSCLK divide-down factor to determine the SDRAM refresh rate. The REF_RATE must be configured prior to setting the SDRAM_EN. A zero value will effectively disable refresh. For Example, if the SDRAM requires 4K refreshes in 64 ms with a SYSCLK of 50 MHz, the REF_RATE should be programmed to:
REF _ RATE =
Sys _ Clk 50MHZ = = 781 = 0 x30 D 4096 (# _ of _ refresh) 64ms (time _ period )
(
)
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Register 0x042 SDRAM Diagnostics Bit 15:1 0 Type N/A R/W Function Unused DIAG_MODE Default 0 0
DIAG_MODE The SDRAM Diagnostic Mode (DIAG_MODE) allows the microprocessor to access the SDRAM for Diagnostic test purposes. While in diagnostic mode, the normal SDRAM accesses are inhibited and the S/UNI-IMA-8 will not operate properly. 0) Diagnostic access is disabled and the S/UNI-IMA-8 operates normally. 1) Diagnostic access is enabled. The SDRAM may be accessed via indirect access as described in section 11.4 using registers 0x44-0x50.
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Register 0x044: SDRAM DIAG Burst RAM Indirect Access Bit 15 14:5 4:0 Type R/W N/A R/W Function BR_BUSY Unused BR_ADDR[4:0] Default 0 N/A 0
Writing to this register triggers an indirect RAM access. See 12.6.1 for further details about operation. BR_ADDR [4:0]: The Burst-ram address number (BR_ADDR [4:0]) indicates the RAM address to be configured or interrogated. The Burst ram is divided into 2 segments: the first is Burst Write RAM, which is used to store data to be loaded into the External SDRAM; the second is the Burst Read RAM, which is used to collect data read from the External SDRAM. The access to bust-write RAM is always a write operation while the access to burst-read RAM is always a read operation. See Figure 24 for the format of the Burst Ram.
* *
0x00-0x0F: Burst-Write RAM 0x10-0x1F: Burst-Read RAM
BR_BUSY: The indirect access command bit (BR_BUSY) reports the progress of an indirect access. BR_BUSY is set high when the register is written to trigger an indirect access; it will stay high until the access is complete. Once the access is complete, the BR_BUSY signal is reset. This register should be polled: (1) to determine when data from an indirect read operation is available in the SDRAM Indirect Burst RAM Data register or (2) to determine when a new indirect write operation may commence.
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Register 0x046: SDRAM DIAG Indirect Burst Ram Data LSB Bit 15:0 Type R/W Function BR_DATA_LSB Default 0
This register should not be written while the BR_BUSY bit is set in the SDRAM Burst RAM Indirect Access register. BR_DATA_LSB: The BR_DATA_LSB represents either: (1) the least significant 16 bits of the data to be written to internal memory or (2) the least significant 16 bits of the read data resulting from the previous read operation. The read data is not valid until after the BR_BUSY bit has been cleared. Register 0x048: SDRAM DIAG Indirect Burst RAM Data MSB Bit 15:0 Type R/W Function BR_DATA_MSB Default 0
This register should not be written while the BR_BUSY bit is set in the SDRAM Burst RAM Indirect Access register. BR_DATA_MSB: The BR_DATA_MSB represents either: (1) the most significant 16 bits of the data to be written to internal memory or (2) the most significant 16 bits of the read data resulting from the previous read operation. The read data is not valid until after the BR_BUSY bit has been cleared. The following explains the Burst RAM accessed by the indirect access. Burst RAM: The microprocessor has access to the external SDRAM for diagnostic testing. There is a 64-byte cell buffer for writing to the external SDRAM and a 64-byte cell buffer for storing data read from the external SDRAM. Figure 24 shows the format of the cell in the Burst RAM. Figure 24 -Burst RAM Format Word # 31 Bits 0
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0x00 0x01 ... ... 0x0F 0x10 0x11 ... ... 0x1F
Burst Write (0) Burst Write (1)
Burst Write(15) Burst Read (0) Burst Read (1)
Burst Read(15)
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Register 0x04A: SDRAM DIAG WRITE CMD 1 Bit 15:0 Type R/W Function WR_BUFFER_ADDR[15:0] Default 0
WR_BUFFER_ADDR[15:0] Indicates the lower 16 bits of the addresses of the cell buffer to write. SDRAM DIAG Write CMD 2 provides the upper address bit and triggers the burst access to happen. Register 0x04C: SDRAM DIAG WRITE CMD 2 Bit 15 14:1 0 R/W Type R Function WRBUSY Unused WR_BUFFER_ADDR[16] 0 Default 0
A write to the SDRAM DIAG WR_CMD 2 register will trigger a transfer of data from the Write Burst Ram to the external SDRAM. The lower bits of the address of the cell buffer in the external SDRAM are given in the SDRAM DIAG WRITE CMD 1 register. WR_BUFFER_ADDR[16] Indicates the upper bit of the addresses of the cell buffer to write. SDRAM DIAG Write CMD 1 provides the lower address bits. WRBUSY The Write Busy bit (WRBUSY) reports the progress of the write access to SDRAM. WRBUSY is set high when this register is written; this triggers the SDRAM access; it stays high until the access is complete. At which point, WRBUSY will be set low. This register should be polled to determine when a new diagnostic write operation may commence. While the WRBUSY bit is set, no indirect accesses to the write burst ram should be performed.
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Register 0x04E: SDRAM DIAG READ CMD 1 Bit 15:0 Type R/W Function RD_BUFFER ADDR[15:0] Default 0
RD_BUFFER_ADDR[15:0] Indicates the lower 16 bits of the addresses of the cell buffer to read. SDRAM DIAG Read CMD 2 provides the upper address bit and triggers the burst access to happen. Register 0x050: SDRAM DIAG READ CMD 2 Bit 15 14:1 0 R/W Type R Function RDBUSY Unused RD_BUFFER ADDR[16] Default 0
A write to the SDRAM DIAG READ CMD 2 register will trigger a transfer of data from the external SDRAM to the Read Burst Ram. The lower bits of the address of the cell buffer in the external SDRAM are given in the SDRAM DIAG READ CMD 1 register. RD_BUFFER_ADDR[16] Indicates the upper bit of the addresses of the cell buffer to read. SDRAM DIAG READ CMD 1 provides the lower address bits. RDBUSY The Read Busy bit (RDBUSY) reports the progress of the read access to SDRAM. RDBUSY is set high when this register is written; this triggers the SDRAM access; it stays high until the access is complete. At which point, RD_BUSY will be set low. This register should be polled to determine when the data is available in the Burst Ram.
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11.5 TC Layer Registers Register 0x060: TTTC Indirect Status Bit 15 14 13:7 6:5 4:0 R/W R/W Type R R/W Function LBUSY LRWB Unused Reserved LINK[4:0] Default 0 0 0 0 0
This register provides the link number used to access the link-provision RAM of the transmit TC processor. Writing to this register triggers an indirect link register access. LINK[4:0], The LINK[4:0] are used to specify the link to be configured or interrogated in the indirect link access. Valid values for the LINK fieldshould range from 0x0 to 0x7. LRWB: The link indirect access control bit (LRWB) selects between either a configure (write) or interrogate (read) access to the link-context RAM. Writing a logic 0 to LRWB triggers an indirect write operation. Data to be written is taken from the Indirect Link Data registers. Writing a logic 1 to LRWB triggers an indirect read operation. The read data can be found in the Indirect Link Data registers. LBUSY: The indirect link access status bit (LBUSY) reports the progress of an indirect access A write to the Indirect Link Address register triggers an indirect access and sets LBUSY to logic 1; it will remain logic 1 until the access is complete. This register should be polled to determine either: (1) when data from an indirect read operation is available in the Indirect Link Data registers or (2) when a new indirect write operation may commence. The LBUSY is not expected to remain at logic 1 for more than 86 REFCLK cycles.
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Register 0x062: TTTC Indirect Link Data Register #1 Bit 15:3 2 1 0 R/W R/W R/W Type Function Unused DHCS Reserved DSCR Default 0 0 0 0
This register contains either: (1) data read from the link-provision RAM of the Transmit TC processor after an indirect Link read operation or (2) data to be inserted into the link provision RAM in an indirect Link write operation. DSCR: The indirect scrambling disable bit (DSCR) configures scrambling. The scramble disable bit to be written to the link provision RAM, in an indirect link write operation, must be set up in this register before triggering the write. When DSCR is logic 1, scrambling is disabled. When DSCR is logic 0, the 48 byte payload is scrambled. DSCR reflects the value written until the completion of a subsequent indirect link-read operation. DHCS: The Disable HCS (Header Check Sequence) bit (DHCS) configures the insertion of the HCS in the fifth byte of the cell. The value of DHCS to be written to the link provision RAM, in an indirect link write operation, must be set up in this register before triggering the write. When DHCS is logic 0, the CRC-8 calculation over the first four bytes of the cell overwrites the fifth byte. When DHCS is logic 1, the fifth byte of the cell passes through unmodified. DHCS reflects the value written until the completion of a subsequent indirect link-read operation.
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Register 0x070: RTTC Indirect Link Status Bit 15 14 13 12:7 6:5 4:0 R/W R/W Type R R/W R/W Function LBUSY LRWB DRHCSE Unused Reserved LINK[4:0] Default 0 0 0 0 0 0
This register provides the link number used to access the link-provision RAM of the receive TC processor. Writing to this register triggers an indirect link-register access. LINK[4:0]: The LINK[4:0] is used to specify the link to be configured or interrogated in the indirect link access. Only 8 links are available. Valid values for the LINK field may range from 0x0 to 0x7. DRHCSE: Disable Reset of the HCS Error Count (DRHCSE) disables automatic reset of the HCS Error Counter (HCSERR). When the bit is set to logic 0, automatic reset of the HCS Error Counter is enabled. If an indirect read is initiated (i.e., CRWBs written with logic 1) with DRHCSE logic 0, the HCS Error Counter is reset to zero upon completion of the indirect read. When the DRHCSE bit is set to logic 1, automatic reset of the HCS Error Counter is disabled. An indirect read results in the interrupt status, as well as the HCSERR count, being read (and possibly cleared). In this situation, the DRHCSE bit is useful for separating interrupt processing from HCSERR count accumulation because it can disable the HCSERR count reset when querying for interrupts. LRWB: The Link indirect access control bit (LRWB) selects between a configure (write) or interrogate (read) access to the Link context RAM. Writing a logic 0 to LRWB triggers an indirect write operation. Data to be written is taken from
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the Indirect Link Data registers. Writing a logic 1 to LRWB triggers an indirect read operation. The read data can be found in the Indirect Link Data registers. LBUSY: The indirect access status bit (LBUSY) reports the progress of an indirect access. A write to the Indirect Link Address register triggers an indirect access and sets LBUSY to logic 1. LBUSY stays high until the access is completed. At which point, LBUSY will be set low. This register should be polled to determine either: (1) when data from an indirect read operation is available in the Indirect Data register or (2) when a new indirect write operation may commence.
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Register 0x072: RTTC Indirect Link Data Register #1 Bit 15:11 10 9 8 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Type Function Unused LCDOOCDPASS HCSPASS UNASSPASS IDLEPASS DDSCR Reserved DDELIN OOCDE HCSE FOVRE LCDE 0 0 0 0 0 0 0 0 0 0 0 Default
This register contains either: (1) data read from the Link provision RAM after an indirect Link read operation or (2) data to be inserted into the Link provision RAM in an indirect Link write operation. The bits to be written to the Link provision RAM, in an indirect Link write operation, must be set up in this register before triggering the write. The bits reflect the value written until the completion of a subsequent indirect Link read operation. The reset state of the bits enables standard ATM cell processing as stipulated in ITU-T Recommendation I.432.1 LCDE: The LCDE bit enables the generation of an interrupt due to a change in the LCD state. When LCDE is set to logic 1, the interrupt is enabled. FOVRE: The FOVRE bit enables the generation of an interrupt due to a FIFO overrun error condition. When FOVRE is set to logic 1, the interrupt is enabled.
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HCSE: The HCSE bit enables the generation of an interrupt due to the detection of an HCS error. When HCSE is set to logic 1, the interrupt is enabled. OOCDE: The OOCDE bit enables the generation of an interrupt due to a change in the cell delineation state. When OOCDE is set to logic 1, the interrupt is enabled. DDELIN: The indirect disable delineate enable bit (DDELIN) configures the TC processor to perform cell delineation and header error detection on the incoming data stream. When DDELIN is set to logic 0, the cell alignment is established and maintained on the incoming data stream. When DDELIN is set to logic 1, the RTTC does not perform any processing on the incoming stream, but passes data through transparently. DDSCR: The DDSCR bit controls the descrambling of the cell payload with the polynomial x43 + 1. When DDSCR is set to logic 1, cell payload descrambling is disabled. When DDSCR is set to logic 0, payload descrambling is enabled. IDLEPASS: The IDLEPASS bit controls the function of the idle cell filter. When IDLEPASS is written with a logic 0, all idle cells (i.e., the first four bytes of a cell: x00, x00, x00, and x01) are filtered out. When IDLEPASS is logic 1, idle cells are passed to the external cell buffer. UNASSPASS: When UNASSPASS is written with a logic 0, all unassigned cells (i.e., the first four bytes of a cell: x00, x00, x00, and x00) are filtered out. When UNASSPASS is logic 1, unassigned cells are passed to on the external cell buffer. HCSPASS: The HCSPASS bit controls the dropping of cells based on the detection of an HCS error. When HCSPASS is logic 0, cells containing an HCS error are dropped. When HCSPASS is a logic 1, cells are passed to the external cell buffer regardless of errors detected in the HCS.
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LCDOOCDPASS: The LCDOCDPASS bit controls the dropping of cells based on the detection of an out of cell delineation and loss of cell delineation. When LCDOOCDPASS is logic 0, cells containing an OOCD error and an LCD error are dropped. When LCDOOCDPASS is a logic 1, cells are passed to the external cell buffer regardless of errors detected in the OOCD and LCD.
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Register 0x074: RTTC Indirect Link Data Register #2 Bit 15:6 5 4 3 2 1 0 R R R R R R Type Function Unused OOCDV LCDV OOCDI HCSI FOVRI LCDI 1 0 0 0 0 0 Default
This register contains data read from the Receive TC Processor Link provision RAM after an indirect read operation. LCDI: The LCDI bit is set high when there is a change in the loss of cell delineation (LCD) state. This bit is reset immediately after a read to this register. FOVRI: The FOVRI bit is set to logic 1 when a FIFO overrun occurs. This bit is reset immediately after a read to this register. HCSI: The HCSI bit is set high when an HCS error is detected. This bit is reset immediately after a read to this register. OOCDI: The OOCDI bit is set high when the logical Link enters or exits the SYNC state. The OOCDV bit indicates whether the logical Link is in the SYNC state or not. The OOCDI bit is reset immediately after a read to this register. LCDV: The LCDV bit gives the Loss of Cell Delineation state. When LCD is logic 1, an out of cell delineation (OCD) defect has persisted for the number of cells specified in the LCD Count Threshold register. When LCD is logic 0, no OCD has persisted for the number of cells specified in the LCD Count Threshold
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register. The cell time period can be varied by using the LCDC[7:0] register bits in the LCD Count Threshold register. OOCDV: The OOCDV bit is high when the logical Link is not currently in the SYNC state.
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Register 0x076: RTTC Indirect Link Data Register #3 Bit 15:0 Type R Function HCSERR[15:0] Default 0
This register contains data read from the Receive TC Processor Link provision RAM after an indirect read operation. HCSERR[15:0]: The HCSERR[7:0] bits indicate the number of HCS error events that occurred during the last accumulation interval. When the number of HCS error events during the last accumulation interval exceeds 64K, the HCSERR[15:0] retains a value of FFFFH until the next accumulation interval (HCSERR[15:0] is reset).
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Register 0x078: LCD Count Threshold Bit 15:8 7:0 R/W Type Function Unused LCDC[7:0] 0x68 Default
LCDC[7:0]: The LCDC[7:0] bits represent the number of consecutive cell periods the receive cell processor must be out of cell delineation before loss of cell delineation (LCD) is declared. Likewise, LCD is not deasserted until the receive cell processor is in cell delineation for the number of cell periods specified by LCDC[7:0]. The default value of LCDC[7:0] is 104; this translates to 28 ms at 1.5 Mbps. 11.6 Line Clock/Data Interface Register 0x100: RCAS Indirect Link and Time-slot Select Bit 15 14 13:11 10:8 7:5 4:0 R/W Type R R/W R/W R/W Function BUSY RWB Unused LINK[2:0] Unused TSLOT[4:0] Default X 0 0 0 X 00
This register provides the link number and time-slot number used to access the timeslot provision RAM. Writing to this register triggers an indirect register access. TSLOT[4:0]: The indirect time-slot number bits (TSLOT[4:0]) indicate the time-slot to be configured or interrogated in the indirect access. For a channelized T1 link, time-slots 1 to 24 are valid. For a channelized E1 link, time-slots 1 to 31 are valid. For unchannelized links, only time-slot 0 is valid.
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LINK[2:0]: The indirect link number bits (LINK[2:0]) select amongst the 8 receive links to be configured or interrogated in the indirect access. RWB: The indirect access control bit (RWB) selects between a configure (write) or interrogate (read) access to the timeslot provision RAM. The address to the timeslot provision RAM is constructed by concatenating the TSLOT[4:0] and LINK[2:0] bits. Writing a logic zero to RWB triggers an indirect write operation. Data to be written is taken from the PROV, the VLDLBEN, and the VLINK[2:0] bits of the Indirect Link Data register. Writing a logic one to RWB triggers an indirect read operation. Addressing of the RAM is the same as in an indirect write operation. The data read can be found in the PROV, the VLDLBEN, and the VLINK[2:0] bits of the Indirect Link Data register. BUSY: The indirect access status bit (BUSY) reports the progress of an indirect access. BUSY is set high when this register is written; this is done to trigger an indirect access, and will stay high until the access is complete. At which point, BUSY will be set low. This register should be polled to determine either: (1) when data from an indirect read operation is available in the Indirect Data register or (2) when a new indirect write operation may commence.
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Register 0x102: RCAS Indirect Link Data Bit 15:10 9 8 7:3 2:0 R/W Type R R/W R/W Function Unused VLDLBEN PROV Unused VLINK[2:0] Default X 0 0 X 00
This register contains either: (1) the data read from the timeslot-provision RAM after an indirect read operation or (2) the data to be inserted into the timeslotprovision RAM during an indirect write operation. The timeslot provision ram maps either timeslots from the physical links or entire physical links to a virtual link number (VLINK). It also provisions timeslots/links and enables the internal loopback feature. VLINK[2:0] The indirect data bits (VLINK[2:0]) report the virtual link number read from the timeslot provision RAM after an indirect read operation has been completed. The virtual link number to be written to the timeslot-provision RAM in an indirect write operation must be set up in this register before triggering the write. VLINK[2:0] reflects the value written until the completion of a subsequent indirect read operation. For proper operation, timeslots in a single link may only be mapped to a single link; in addition, only VLINK values of 0 - 0x7 are valid. PROV The indirect provision enable bit (PROV) reports the timeslot provision enable flag read from the timeslot provision RAM after an indirect read operation has been completed. The provision enable flag to be written to the timeslot provision RAM in an indirect write operation must be set up in this register before triggering the write. When PROV is set high, the current receive data byte is processed as part of the virtual link (as indicated by VLINK[2:0]). When PROV is set low, the current time-slot does not belong to any virtual link and the receive data byte is ignored. PROV reflects the value written until the completion of a subsequent indirect read operation.
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VLDLBEN The indirect virtual link based diagnostic loopback enable bit (VLDLBEN) reports the loopback enable flag read from the timeslot provision RAM after an indirect read operation has been completed. The loopback enable flag to be written to the timeslot provision RAM in an indirect write operation must be set up in this register before triggering the write. When VLDLBEN is set high, the current receive data byte is to be over-written by data retrieved from the loopback FIFO of the virtual link as indicated by VLINK[2:0]. When VLDLBEN is set low, the current receive data byte is processed normally. VLDLBEN reflects the value written until the completion of a subsequent indirect read operation.
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Register 0x104: RCAS Framing Bit Threshold Bit 15:7 6:0 Type R R/W Function Unused FTHRES[6:0] Default X 0x3F
This register contains the threshold used by the clock-activity monitor to detect framing bits/bytes. FTHRES[6:0] The framing bit threshold bits (FTHRES[6:0]) contain the threshold used by the clock activity monitor to detect for the presence of framing bits. A counter in the clock-activity monitor increments at each REFCLK and is cleared by a rising edge of the RSCLK. When the counter exceeds the threshold given by FTHRES[6:0], a framing bit/byte has been detected. FTHRES[6:0] should be set as a function of the REFCLK period and the expected gapping width of RSCLK during framing bits/bytes.
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Register 0x106: RCAS Link Disable Bit 15 14:3 2:0 R/W Type R Function VLDIS Unused DVLINK[2:0] Default 0 X 0
This register allows the squelching of output data from a particular virtual link. DVLINK[2:0]: The disable virtual link bits (DVLINK[2:0]) specify the virtual link whose output data from the RCAS are to be squelched. When VLDIS is set high, the virtual link specified by DVLINK[2:0] is disabled, even if the virtual link is provisioned. VLDIS: When set high, the virtual link disable bit (VLDIS) squelches valid data on the output of RCAS for the virtual link indicated by DVLINK[2:0].
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Register 0x140- 0x14E: RCAS Link #0 to Link #7 Configuration Bit 15:3 2 1 0 Type R R/W R/W R/W Function Unused Reserved E1 CEN Default X 0 0 0
This register configures operational modes of receive link #0 to link #7 (RSDATA[N]/ RSCLK[N] where 0 N 7). CEN: The channelize enable bit (CEN) configures link #N for channelized operation. RSCLK[N] is held low during the T1 framing bit and during the E1 framing byte. The data bit on RSDATA[N] that is clocked in by the first rising edge of RSCLK[N] after an extended low period is considered to be the most significant bit of time-slot 1. When CEN is set low, link #N is unchannelized. The E1 register bit is ignored. RSCLK[N] is gapped during non-data bytes. All data bits are treated as a contiguous stream with arbitrary byte alignment. E1: The E1 frame structure select bit (E1) configures link #N for channelized E1 operation when CEN is set high. RSCLK[N] is held low during the FAS and NFAS framing bytes. The data bit on RSDATA[N] that is associated with the first rising edge of RSCLK[N] after an extended low period is considered to be the most significant bit of time-slot 1. Link data is present at time-slots 1 to 31. When E1 is set low and CEN is set high, link #N is configured for channelized T1 operation. RSCLK[N] is held low during the framing bit. The data bit on RSDATA[N] that is associated with the first rising edge of RSCLK[N] after an extended low period is considered to be the most significant bit of time-slot 1. Link data is present at time-slots 1 to 24. E1 is ignored when CEN is set low.
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Register 0x180: TCAS Indirect Link and Time-slot Select Bit 15 14 13:11 10:8 7:5 4:0 R/W R/W Type RO R/W Function Busy RWB Unused LINK[2:0] Unused TSLOT[4:0] Default X 0 X 0 X 0
This register provides the link number and time-slot number used to access the timeslot provision RAM. Writing to this register triggers an indirect register access and transfers the contents of the Indirect Link Data register to an internal holding register. TSLOT[4:0] The indirect time-slot number bits (TSLOT[4:0]) indicate the time-slot to be configured or interrogated in the indirect access. For a channelized T1 link, time-slots 1 to 24 are valid. For a channelized E1 link, time-slots 1 to 31 are valid. For unchannelized links, only time-slot 0 is valid. LINK[2:0] The indirect link number bits (LINK[2:0]) select amongst the 8 transmit links to be either configured or interrogated in the indirect access. RWB The indirect access control bit (RWB) selects between a configure (write) or interrogate (read) access to the timeslot provision RAM. The address to the timeslot provision RAM is constructed by concatenating the TSLOT[4:0] and LINK[4:0] bits. Writing a logic zero to RWB triggers an indirect write operation. Data to be written is taken from the PROV and the VLINK[2:0] bits of the Indirect Data register. Writing a logic one to RWB triggers an indirect read operation. Addressing of the RAM is the same as in an indirect write operation. The data read can be found in the PROV and the VLINK[2:0] bits of the Indirect Link Data register after the BUSY bit has cleared.
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BUSY The indirect access status bit (BUSY) reports the progress of an indirect access. BUSY is set high when this register is written to trigger an indirect access, and will stay high until the access is complete. At which point, BUSY will be cleared (low). Alternatively, BUSY will be set high when TCAS first comes out of reset until the RAM has been initialized. This register should be polled to determine either: (1) when data from an indirect read operation is available in the Indirect Data register or (2) when a new indirect write operation may commence. Any indirect operation that is initiated while BUSY is still high will be corrupted.
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Register 0x182: TCAS Indirect Channel Data Bit 15:9 8 7:3 2:0 R/W R/W Type Function Unused PROV Unused VLINK[2:0] Default X 0 X 0
This register contains either: (1) the data read from the timeslot provision RAM after an indirect read operation or (2) the data to be inserted into the timeslot provision RAM in an indirect write operation. The timeslot provision ram maps either timeslots from the physical links or entire physical links to a virtual link number (VLINK). It also provisions timeslots/links VLINK[2:0] The indirect data bits (VLINK[2:0]) report the channel number read from the timeslot provision RAM after an indirect read operation has been completed. The channel number to be written to the timeslot provision RAM in an indirect write operation must be set up in this register before triggering the write. VLINK[2:0] reflects the last value either read or written until the completion of a subsequent indirect read operation. PROV The indirect provision enable bit (PROV) reports the timeslot provision enable flag read from the timeslot provision RAM after an indirect read operation has been completed. The provision enable flag to be written to the timeslot provision RAM in an indirect write operation must be set up in this register before triggering the write. When PROV is set high, the current time-slot is assigned to the virtual link as indicated by VLINK[2:0]. When PROV is set low, the time-slot does not belong to any virtual link. The transmit link data is set to the contents of the Idle Time-slot Fill Data register. PROV reflects the last value read or written until the completion of a subsequent indirect read operation.
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Register 0x184: Framing Bit Threshold Bit 15:7 6:0 R/W Type Function Unused FTHRES[6:0] Default X 0x1F
This register contains the threshold used by the clock activity monitor to detect for framing bits/bytes. FTHRES[6:0] The framing bit threshold bits (FTHRES[6:0]) contains the threshold used by the clock activity monitor to detect the presence of framing bits. A counter in the clock activity monitor increments at each REFCLK and is cleared by a rising edge of the TSCLK. When the counter exceeds the threshold given by FTHRES[6:0], a framing bit/byte has been detected. FTHRES[6:0] should be set as a function of the REFCLK period and the expected gapping width of TSCLK during framing bits/bytes.
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Register 0x186: TCAS Idle Time-slot Fill Data Bit 15:8 7:0 R/W Type Function Unused FDATA[7:0] Default X 0xFF
This register contains the data to be written to the disabled time-slots of a channelized link. FDATA[7:0] The fill data bits (FDATA[7:0]) are transmitted during disabled (PROV set low) time-slots or virtual links.
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Register 0x188: TCAS Channel Disable Register Bit 15 14:3 2:0 R/W Type R/W Function VLDIS Unused DVLINK[2:0] Default 0 X 0
This register indicates a virtual link that is to be disabled (unprovisioned) while individual time-slots are changed. This allows virtual links to either turn on or off at once instead of gradually while each time-slot in the provisioning RAM is written. DVLINK[2:0] The disable virtual link bits (DVLINK[2:0]) indicate the virtual link to be disabled. If the CHDIS bit is set high, all time-slots assigned to this virtual link will be forced unprovisioned, and the value in FDATA[7:0] will be transmitted. VLDIS The virtual link disable bit (VLDIS) disables the virtual link in DVLINK[2:0]. When VLDIS is set high, all time-slots assigned to the virtual link in DVLINK[2:0] will be forced unprovisioned, and the PROV bit of those timeslots will be ignored. When CHDIS is low, the virtual link's provisioning state is set by the PROV bit.
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Register 0x1C0 - 0x1CE: TCAS Link #0 to Link #7 Configuration Bit 15:3 2 1 0 R/W R/W R/W Type Function Unused Reserved E1 CEN Default X 0 0 0
This register configures the operational modes of transmit link #0 to link #7 (TSDATA[N] / TSCLK[N]; where 0 N 7=). CEN The channelize enable bit (CEN) configures link #N for channelized operation. TSCLK[N] is held low during the T1 framing bit or the E1 framing byte. Thus, on the first rising edge of TSCLK[N] after the extended low period, a downstream block can sample the MSB of time-slot 1. When CEN is set low, link #N is unchannelized and the E1 register bit is ignored. TSCLK[N] can be gapped during non-data bytes, and all data bits are treated as a contiguous stream without regard to time-slots. E1 The E1 frame structure select bit (E1) configures link #N for channelized E1 operation when CEN is set high. TSCLK[N] is held low during the FAS and NFAS framing bytes. The most significant bit of time-slot 1 is placed on TSDATA[N] on the last falling edge of TSCLK[N] ahead of the extended low period. Link data is present at time-slots 1 to 31. When E1 is set low and CEN is set high, link #N is configured for channelized T1 operation. TSCLK[N] is held low during the framing bit. The MSB of time-slot 1 is placed on TSDATA[N] on the last falling edge of TSCLK[N] ahead of the extended low period. Link data is present at time-slots 1 to 24. E1 is ignored when CEN is set low.
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11.7 RIPP Registers Register 0x200:RIPP Control Bit 15 14 13 12: 0 RIPP_BUSY This is a status signal indicating that the RIPP main-state machine is currently active. This bit is generated by RIPP. RIPP_EN The RIPP_EN enables the RIPP main state machine for normal operations. When RIPP_EN = 0 and RIPP_BUSY = 0, all RIPP operations are disabled. The RIPP_EN should be set to a `1' for normal operations after the initialization of RIPP context memory. Type R/W R/W R Function RIPP_EN Reserved RIPP_BUSY Reserved Default 0 0 0 0
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Register 0x202:RIPP Indirect Memory Access Control Bit 15 14 13 12:10 9:0 R/W Type RO R/W R/W Function MEM_BUSY MEM_RWB MEM_SEL Reserved MEM_ADDR 0 Default 0 0 0
This register controls the indirect access to the internal memory area. There are two separate RAMs used by RIPP. One is the configuration memory, which holds the configuration information for all groups and links programmed by the microprocessor; the other is the context memory, which stores the state context used as the working space for the RIPP internal state machine. Each of them is 32-bits wide and contains 1024 words. MEM_ADDR: The indirect memory address (MEM_ADDR [9:0]) indicates the memory word address to be read or written. The memory-address organization of the internal RAMs is shown in Table 6 and Table 7. Table 6 Configuration Memory Address Space Description Group configuration record area. Reserved TX link configuration record area. Reserved RIPP RX Link Configuration Record area. Reserved
Address space 0x000 - 0x03F 0x040 - 0x29F 0x2A0 - 0x2A7 0x2A8 - 0x34F 0x350 - 0x357 0x358 - 0x3FF
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Table 7
Context Memory Address Space Description Group context record area. Reserved TX link context record area. Reserved RX link context record area. Reserved
Address space 0x000 - 0x03F 0x040 - 0x29F 0x2A0 - 0x2AF 0x2B0 - 0x34F 0x350 - 0x35F 0x360 - 0x3FF MEM_SEL:
The memory select (MEM_SEL) is used to select between the two internal RAMs. A logic `0' selects the configuration memory, while a logic `1' selects the context memory. MEM_RWB: The memory indirect access control bit (MEM_RWB) selects between a configure (write) or interrogate (read) access to the RIPP internal context RAM. Writing a logic 0 to MEM_RWB triggers an indirect write operation. Data to be written is taken from the RIPP Indirect Memory Data registers. Writing a logic 1 to MEM_RWB triggers an indirect read operation. The read data can be found in the RIPP Indirect Channel Data registers MEM_BUSY: The memory indirect access status bit (MEM_BUSY) reports the progress of an indirect access. To trigger an indirect access, MEM_BUSY is set high when this register is written; it stays high until the access is complete; at that point, MEM_BUSY is set low. This register should be polled to determine either: (1) when data from an indirect read operation is available in the Indirect Data register or (2) when a new indirect write operation may commence.
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Register 0x204 - 0x206:RIPP Indirect Memory Data Register Array Address 0x204 0x206 Bit 15:0 15:0 Type R/W R/W Function MEM_DATA_LSB MEM_DATA_MSB Default 0 0
MEM_DATA_LSB: The MEM_DATA_LSB represents either: (1) the least significant 16 bits of the data to be written to internal memory or (2) the least significant 16 bits of the read data resulting from the previous read operation. The read data is not valid until after the MEM_BUSY bit has been cleared. MEM_DATA_MSB: The MEM_DATA_MSB represents either: (1) the most significant 16 bits of the data to be written to internal memory or (2) the least significant 16 bits of the read data resulting from the previous read operation. The read data is not valid until after the MEM_BUSY bit has been cleared. The actual memory data structure is shown in Table 8 through Table 14. Group Configuration Record Memory Area The group configuration record area is located in the RIPP configuration memory. There are 4 group configuration records that contain the PM programmed configuration data for the corresponding groups. Each record is 16 words deep by 32 bits wide, and is addressed by the group tag number. MEM_ADDR = Area_base_address + Group_tag * 0x10 + Word Offset Table 8 WORD 0 RIPP Group Configuration Record Structure BIT 31:24 DATA FIELD IMA_OAM_LABEL DESCRIPTION IMA OAM label value for the group. This indicates the IMA version for the current group, and is used to compare against the IMA version number carried in octet 6 of the incoming ICP cells.
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23:22
GROUP_SYM_MO DE
Group symmetry mode. This is programmed by PM during group configuration. It is then used by RIPP to compare against the Group Symmetry mode field in the incoming ICP cells during group start-up process. If the two values do not match, the start-up process will be aborted. The supported values for this field are: "00": Symmetrical configuration and operation "10": Symmetrical configuration and asymmetrical operation "10": Asymmetrical configuration and asymmetrical operation "11": Reserved
21
GROUP_ICP_FWD _EN
Group ICP cell forwarding enable. `0': Disable ICP cell forwarding to PM. `1': Enable ICP cell forwarding to PM. An interrupt will be generated upon each ICP cell to be forwarded to PM, and the content of the ICP cell will be copied to microprocessor's directly accessible registers.
20
Group_ICP_FWD_Fi Group ICP cell forwarding filtering lter enable. `0': No filtering. All ICP cells from RDAT will be forwarded to PM. `1': Filtering. RIPP will filter out the ICP cells which carry no new information (determined by the SCCI field) before forwarding to PM.
19
IMA_10_ENABLE
IMA version 1.0 style link state reporting enable. This field selects how the link state field in the incoming
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and outgoing ICP cells should be interpreted. Note that this bit will be ignored if the group is in asymmetric configuration mode. `0': IMA version 1.1 style (default) `1' IMA version 1.0 style. 18:10 9 RESERVED PM_ADJUST_DELA Y_DONE_INT_EN PM adjust delay procedure done Interrupt enable `0' Interrupt not enabled `1' Interrupt enabled. 8 FE_TRL_INT_EN Invalid RX TRL Interrupt enable `0' Interrupt not enabled `1' Interrupt enabled. 7 GROUP_TIMING_I NT_EN Group timing interrupt enable `0' Interrupt not enabled `1' Interrupt enabled. 6 FE_TIMEOUT_INT_ EN FE Timeout Interrupt Enable: `0' Interrupt not enabled `1' Interrupt enabled. 5 GROUP_TIMEOUT _INT_EN Group Timeout Enable. `0' Interrupt not enabled `1' Interrupt enabled. 4 FE_ABORT_INT_E N FE Abort Interrupt Enable. `0' Interrupt not enabled `1' Interrupt enabled. 3 NE_ABORT_INT_E N NE Abort Interrupt Enable `0' Interrupt not enabled `1' Interrupt enabled. 2 GTSM_INT_EN GTSM Interrupt Enable
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`0' Interrupt not enabled `1' Interrupt enabled. 1 FE_GSM_INT_EN FE GSM Interrupt Enable `0' Interrupt not enabled `1' Interrupt enabled. 0 NE_GSM_INT_EN NE GSM Interrupt Enable `0' Interrupt not enabled `1' Interrupt enabled. 1 31:24 TX_IMA_ID IMA ID value to use in the TX (outgoing) ICP cells. This field is programmed by PM during group record initialization. 23:22 TX_M Transmit IMA frame length (M). Used by TIMA in the transmit IMA operation. "00": M = 32 "01": M = 64 "10": M = 128 "11": M = 256 21:16 P_TX Minimum number of active TX links required in the group in order for the group to be operational. TX End-to-end channel. This data field is used by RIPP to generate the endto-end channel field in the outgoing ICP cells. Transmit clock mode. "0": ITC mode. "1": CTC mode. This field is used in the outgoing TX ICP cells. Note the actual clock mode used by TIMA may differ from this. After a group is added, this field should not be changed, unless a
15:8
TX_END_CHANNE L
7
TX_CLK_MODE
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group restart is to be issued. 6:0 2 31:25 24 RESERVED RESERVED RX_IMA_ID_CFG_E This bit selects whether the IMA ID N value used in the RX direction should be configured by PM or captured from incoming ICP cells. `0': IMA ID captured from ICP cells and saved in context memory (RX_IMA_ID_CAP). `1': IMA ID configured by PM in the RX_IMA_ID_CFG field in the configuration memory. 23:16 15:14 13:8 RX_IMA_ID_CFG RESERVED P_RX Minimum number of active RX links required in the group in order for the group to be operational. RX IMA ID value programmed by PM.
7:4 3:0
Reserved RX_M_RANGE 4-bit vector indicating the M values deemed acceptable. Used during group parameter negotiation. Bit 3: M = 256 (`0': unacceptable, `1': acceptable) Bit 2: M = 128 (`0': unacceptable, `1': acceptable) Bit 1: M = 64 (`0': unacceptable, `1': acceptable) Bit 0: M = 32 (`0': unacceptable, `1': acceptable)
3
31:26 25:16
RESERVED RX_DELAY_TOL Receive differential Delay tolerance. This field is the maximum allowed amount of delay to be accumulated for
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a link within the group. This threshold will be used in determining if links are acceptable for adding to a group. 16:11 10 RESERVED RX_ADD_DELAY_E N Receive IMA group delay-adding enable. When enabled, the RIPP will roll back the RDAT read pointers, which effectively adds more delay to the group, in order to accommodate the new link if it is necessary. `0': disabled. `1': enabled. 9:0 RX_DELAY_GUAR D_BAND Receive IMA group link differential delay guard-band value. This is the suggested distance between RDAT cell write pointer on the slowest link and the RDAT cell read pointer (expressed in the unit of cells), which is set by RIPP when it activates the RX data path during group start-up Note that this is only a recommended behavior; if necessary, RIPP may choose to not to maintain this guard band in order to accept a slow link. 4 5:15 31:0 31:0 RESERVED RX_PHY_TABLE This table contains the physical link numbers of all RX links assigned to the group by PM. The table has 32 entries that are packed into 11 32-bit words; each entry corresponds to one RX link. The order of links in the table is determined by PM prior to group start-up, and is not related to the LIDs or physical link numbers. See Table 9 for the detailed bit mapping. Note that this table needs to be configured identical to the TX_PHY_TABLE if the group is
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configured in symmetrical configuration mode
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Table 9 Word 0
RX physical link table Bit 31:23 22:20 19:13 12:10 9:3 2:0 Description Reserved RX Physical link pointer 2 Reserved RX Physical link pointer 1 Reserved RX Physical link pointer 0
...... Word 11
..... 31:13 12:10 9:3 2:0 Reserved RX Physical link pointer 31 Reserved RX Physical link pointer 30
RIPP TX Link Configuration Record Memory Area The RIPP TX Link Configuration Record area is located in the RIPP configuration memory. There are 8 RIPP TX Link Configuration Records that contain the PM programmed configuration data for the corresponding TX links. Each record is 1 word deep by 32 bits wide, and is addressed by the physical link number. MEM_ADDR = Area_base_address + physical link number * 0x1+ Word Offset
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Table 10 WORD 0
RIPP TX Link Configuration Record Structure BIT 31:28 17:16 DATA FIELD RESERVED TX_LINK_GROUP_ TAG Group tag value of the group which this TX physical link has been assigned to. This field is programmed by PM during link record initialization. 15:11 TX_LID LID value for the physical link. This field is programmed by PM during link record initialization. 10:5 4 RESERVED TX_ACTIVE_INT_E N TX Active interrupt enable. `0' Interrupt not enabled DESCRIPTION
3
`1' Interrupt enabled. FE_RX_UNUSABLE FE RX Unusable interrupt enable. _INT_EN `0' Interrupt not enabled FE_RX_DEFECT_I NT_EN TX_TIMEOUT_INT_ EN RESERVED `1' Interrupt enabled. FE RX Defect interrupt enable. `0' Interrupt not enabled `1' Interrupt enabled. Tx_Timeout interrupt enable. `0' Interrupt not enabled `1' Interrupt enabled.
2
1
0
RIPP RX Link Configuration Record Memory Area The RIPP RX Link Configuration Record area is located in the RIPP configuration memory. There are 8 RIPP RX Link Configuration Records that contain the PM programmed configuration data for the corresponding RX links. Each record is 1 word deep by 32 bits wide, and is addressed by the physical link number.
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MEM_ADDR = Area_base_address + physical link number * 0x1+ Word Offset
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Table 11 WORD 0
RIPP RX Link Configuration Record Structure BIT 31:22 17:16 DATA FIELD RESERVED RX_LINK_GROUP_ TAG Group tag value of the group which this TX physical link has been assigned to. This field is programmed by PM during link record initialization. 15:11 10 RESERVED RX_ACTIVE_INT_E N IDLE_CELL_INT_E N FE_TX_UNUSABLE _INT_EN DIFF_DELAY_INT_ EN LODS_OVERRUN_I NT_EN LODS_UNDERRUN _INT_EN LCD_INT_EN RX Active Interrupt enable. `0' Interrupt not enabled `1' Interrupt enabled. Idle cell interrupt enable. `0' Interrupt not enabled `1' Interrupt enabled. FE TX UNUSABLE Interrupt enable `0' Interrupt not enabled `1' Interrupt enabled. Differential Delay Interrupt enable `0' Interrupt not enabled `1' Interrupt enabled. LODS, DCB overrun Interrupt enable `0' Interrupt not enabled `1' Interrupt enabled. LODS, DCB under- Interrupt enable `0' Interrupt not enabled `1' Interrupt enabled. LCD Interrupt enable `0' Interrupt not enabled `1' Interrupt enabled. LIF Interrupt enable `0' Interrupt not enabled `1' Interrupt enabled. DESCRIPTION
9
8
7
6
5
4
3
LIF_INT_EN
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2
INVALID_ICP_INT_ EN RX_TIMEOUT_INT
1
Invalid_ICP interrupt enable `0' Interrupt not enabled `1' Interrupt enabled. Rx Timeout Interrupt enable. `0' Interrupt not enabled `1' Interrupt enabled.
0
RESERVED
RIPP Group Context Record Memory Area The group context record area is located in the RIPP context memory. There are 4 group context records that contain the current state machine states and status information for the corresponding groups. Each record is 16 words deep by 32 bits wide, and is addressed by the group tag number. MEM_ADDR = Area_base_address + Group_tag * 0x10 + Word Offset Unless otherwise specified, all data and the reserved fields should be cleared (to all `0's) by PM prior to adding the group; they will be cleared by RIPP during a group restart process Table 12 WORD 0 RIPP Group Context Record Structure BIT 31 DATA FIELD GROUP_EN DESCRIPTION Indicates if the current group is enabled. This bit is set by PM using the add_group command, and cleared by PM using the delete_group command. `0': not enabled (group in NOT_CONFIGURED state) `1': the group is enabled and currently active. This field will remain at its current value during a group-restart. 30:27 GSM Group state machine state. "0000": Start-up
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"0001": Start-up-Ack "0010": Config-Aborted - Unsupported M "0011": Config-Aborted - Incompatible group symmetry "0100": Config-Aborted - Unsupported IMA versions "0111": Config-Aborted - Other reasons "1000": Insufficient-links "1001": Blocked "1010": Operational Others: Reserved 26:24 23 RESERVED GTSM Group traffic state machine state "0": down (no ATM data transmission is allowed) "1": up (ATM data transmission is allowed) 22:21 GWP_Active Group wide procedure in progress. "00": No group-wide procedure is currently in progress. "01": Group start-up procedure is in progress. "10": LASR is in progress. Others: reserved 20 19 reserved LSM_SYNC_TRAN S Indicates whether there has been a transition on the LSM_SYNC state machine in the last processing cycle for the group. `0': There was no transition. `1': There was a transition.
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18:16
LSM_SYNC
Current state of LSM_SYNC state machine, which is used to synchronize LSM transition during group startup and LASR procedure. "000": IDLE "001": LSM_SYNC_GETM (Group parameter negotiation finished). "010": LSM_SYNC_RX_USABLE (RX ready to go to usable state, delay evaluation needed). "011": LSM_SYNC_RX_ACTIVE_RDAT (RX ready to start receiving, starting RDAT and IDCC) "100": LSM_SYNC_RX_ACTIVE (RX ready to report ACTIVE to FE) "101": LSM_SYNC_TX_ACTIVE (TX ready to report active to FE) Far-end GSM states. This is copied from the group state field in the incoming ICP cells
15:12
FE_GSM
11:6 5:0 1 31
NUM_TX_LINKS_A Total number of tx links that are CTIVE currently in an active state. NUM_RX_LINKS_ ACTIVE GROUP_TIMER_E N1 Total number of rx links that are currently in an active state. Group timer 1 enable. The enable bit is set when the timer is loaded; it is cleared when either a timeout occurs or the timer is disabled. Group-level timer 1. Implemented as 4bit down counter. The counter is loaded with the appropriate timeout value when the timer is enabled, and decrements on every timer tick, until it reaches zero. A timeout event is
30:28 27:24
RESERVED GROUP_TIMER1
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declared when a timer tick occurs and the counter equals zero, if the timer is enabled. 23 GROUP_TIMER_E N2 Group timer 2 enable. The enable bit is set when timer is loaded; it is cleared when either a timeout occurs or the timer is disabled. Group-level timer 2. Implemented as 4bit down counter. The counter is loaded with the appropriate timeout value when the timer is enabled, and decrements on every timer tick, until it reaches zero. A timeout event is declared when a timer tick occurs and the counter equals to zero, if the timer is enabled. Indicates whether there is currently an interrupt active from the group (including all the links). This bit is set to `1' by RIPP upon generating a interrupt and cleared upon PM issuing a read_event command. No new interrupt will be generated once this bit is set. This field will remain at its current value during a group-restart. 14 GROUP_INHIBIT_ STATUS Group inhibiting status. `0': Group is not inhibited. `1': Group is inhibited. This field can be programmed by PM during group record initialization, and can be modified later using inhibit_group/not_inhibit_group commands. Note it is possible to inhibit the group before actually issuing the
22:20 19:16
RESERVED GROUP_TIMER2
15
GROUP_INT_ACTI VE
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add_group command. This field will remain at its current value during a group-restart. 13 12 RESERVED FE_TRL_STATUS TRL specified in the last receive ICP cell is a link that is "in_group". If the TRL received in the last ICP cell in not "in_group",, this bit is be cleared, and the TRL remains with the last specified valid TRL. During the period in which the specified TRL is not "in_group"i, the scheduling of the cells played out to the ATM layer is not accurate and the depth of the DCB buffers may drift and cause DCB buffer overruns or underruns. If on group startup, the TRL is not detected to be "in_group", the group will not start up. Group timing error. The FE IMA transmit clock mode does not match the NE transmit clock mode. PM adjust_delay procedure done interrupt. The adjust_delay procedure invoked by the PM command has successfully finished or aborted. FE TRL Interrupt. TheFE_TRL_STATUS bit has changed state. Group timing interrupt. The the GROUP_TIMING_ERROR has changed state. Startup-Ack Timeout: The FE fails to transition into the STARTUP-ACK state prior to the NE timing out. GSM fails to come out of Insufficientlinks state during a group start-up procedure before the relevant timer
11
GROUP_TIMING_ ERROR RESERVED PM_ADJUST_DEL Y_INT
10 9
8
FE_TRL_INT
7
GRP_TIMING_INT
6
FE_TIMEOUT_INT
5
GR_TIMEOUT_INT
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4 3
FE_ABORT_INT NE_ABORT_INT
expires. FE entered CONFIG-ABORTED state during group start-up. Entered NE Config aborted state. FE group parameters unacceptable during group start-up. Possible causes are IMA OAM label proposed by FE not acceptable. Group symmetry proposed by FE not acceptable. RX M proposed by FE not acceptable GTSM state change. FE GSM state change. NE GSM state change. Current TX SCCI value for the group. Each time the Tx ICP cell class B&C info changes, the SCCI field increments by one. This field will remain at its current value during a group-restart.
2 1 0 2 31:24
GTSM_INT FE_GSM_INT NE_GSM_INT TX_SCCI
23:16
TX_RX_TEST_PT N
Tx test pattern field to be sent in the transmit ICP cell. If the test link command active bit in the incoming ICP cell from RDAT is set, this field is updated using the TX test pattern field in the same ICP cell; otherwise this field is set to "FF" internally. This field will remain at its current value during a group-restart.
15:3 2:0
RESERVED TX_TRL_PHY_ID Physical link ID for TX TRL. This field need to be programmed by PM prior to group startup to ensure TX IDCC ticks are generated and TIMA start sending ICP cells once the group is added.
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Once a group is added, the TRL can be changed by using UPDATE_TX_TRL command. This field will remain at its current value during a group-restart. 3 31:25 24 RESERVED TX_GSM_2FRAME Indicates whether at least 2 TX frames has been transmitted since the last time we have a gsm change. This is used to make sure the group status and info field stays the same for at least 2 TX frames, as stated in IMA spec. `0': Less than 2 frames have been transmitted since the last GSM transition. `1': At least 2 frames have been transmitted since the last GSM transition. 23:16 TX_LAST_GSM_T RANS_IFSN TX_TEST_EN The TX frame sequence number being transmitted last time there is a GSM transition. Enable Tx test pattern procedure. "0": Disabled. The test pattern field in the outgoing ICP cells will be filled with zeros. "1": Enabled. RIPP will copy the stored Tx_test_pattern info over to the test pattern field. This field is set and changed using the update_test_ptn PM command. This field will remain at its current value during a group-restart. 14:13 12:8 RESERVED TX_TEST_LID Tx LID of the test link.
15
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This field is set and changed using the update_test_ptn PM command. This field will remain at its current value during a group-restart. 7:0 TX_TX_TEST_PTN Tx test pattern field to be sent in the transmit ICP cell. This field is set and changed using the update_test_ptn PM command. This field will remain at its current value during a group-restart. 4 31:0 TX_PHY_VALID 32 bit vector in which each bit corresponds to one TX physical link in TX_PHY_TABLE (which is located in TIMA group context memory). "0": table entry not valid "1": table entry valid (physical link pointed by the corresponding TX_PHY_TABLE entry has been assigned to the current group.) This field will remain at its current value during a group-restart. 5 31:0 TX_LASR_ACT 32 bit vector in which each bit corresponds to one TX physical link in TX_PHY_TABLE (which is located in TIMA group context memory). "0": the link is not involved in LASR. "1": the link is currently involved in a active LASR procedure. 6 31:30 29 RESERVED RX_FE_INFO_VALI This indicates whether the context data D fields captured from incoming ICP cells) or not. `0': Invalid. `1': Valid.
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This bit is set internally by RIPP during group start-up upon capturing the first valid incoming ICP cells. This field will remain at its current value during a group-restart. 28 27:26 RESERVED RX_M Receive IMA frame length (M). This parameter is captured from incoming ICP cells during group-start-up negotiation process, and later used by RDAT in the receive IMA operation. "00": M = 32 "01": M = 64 "10": M = 128 "11": M = 256 25:24 FE_SYM_MODE Group symmetrical mode as indicated by the FE in the latest ICP cell analyzed IMA OAM label value as indicated by the FE in the latest ICP cell analyzed Current RX SCCI value for the group. This value is captured from the incoming ICP cells and used to determine whether the ICP cell should be processed. This field will remain at its current value during a group-restart. 7:0 RX_IMA_ID Stores the RX_IMA_ID. The value may be copied from the RX_IMA_ID_CFG field in the configuration memory if the RX_IMA_ID_CFG_EN bit is set, otherwise it is captured from the first incoming ICP cell after the group is added or restarted. 32 bit vector in which each bit corresponds to one RX physical link in
23:16 15:8
FE_IMA_OAM_LA BEL RX_SCCI
7
31:0
RX_PHY_VALID
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RX_PHY_TABLE. "0": table entry not valid "1": table entry valid (physical link pointed by the corresponding RX_PHY_TABLE entry has been assigned to the current group). This field is cleared by PM during group record initialization. It may be modified during normal operations by issuing the appropriate PM command, such as add_group, add_link, delete_group, delete_link. This field will remain at its current value during a group-restart. 8 31:0 RX_LASR_ACT 32 bit vector in which each bit corresponds to one RX physical link in RX_PHY_TABLE (which is located in RIPP Group configuration memory). "0": the link is not involved in LASR. "1": the link is currently involved in a active LASR procedure. 9 31:0 RX_TEST_PTN_M ATCH 32 bit vector in which each bit corresponds to the current test pattern match result on one RX link. The order of RX links is defined in RX_PHY_TABLE (which is located in the RIPP Group configuration memory). "0": the Rx_test_pattern field in the incoming ICP cells on the link does not match the TX_test_pattern field in the outgoing ICP cells. "1": the Rx_test_pattern field in the incoming ICP cells on the link matches the TX_test_pattern field in the outgoing ICP cells.
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10
31:0
RX_LID_ALLOC
32 bit vector in which each bit indicates whether the LID value represented by the bit index is occupied. For example, Bit 31 corresponds to LID value 31, bit 0 corresponds to LID 0, and so on. `0': LID has not been allocated to any links. `1': LID has been allocated to one of the RX links in the group.
11
31 30:29 28:24 23:3 2:0
RX_TX_TEST_CM D Reserved RX_TX_TEST_LID reserved Last_Scci_phy_link _id
The TX_TEST_CMD field captured from incoming ICP cells. The TX_TEST_LID field captured from incoming ICP cells. Physical link ID of the rx link on which the last "analyzable" ICP cell comes. A ICP cell is considered analyzable if 1). the current processing cycle is ICP and 2). the ICP cell is valid, and 3). the ICP cell carries a new SCCI, or the ICP cell comes from the same link of the last analyzed ICP cell; and 4). RX_IMA_ID matches the configured value (or if no value is configured, the value captured from the first ICP cell if group is started/restarted)
12
31
RX_TRL_VALID
This indicates whether in the RX IDCC the TRL of the current group has been turned on or not. TRL is identified by the RX_TRL_PHY_ID field, which is translated from the TX_TRL_ LID in the incoming ICP cells, after it is validated by RIPP. `0': Invalid. TRL off.
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`1': Valid. TRL on. This bit is set internally by RIPP when it first turns on the TRL in RX IDCC (when LSM_SYNC reaches the right state and TRL LID has been validated). It is possible for the FE to change the TRL_LID during normal operations, in which case the new TRL LID will be verified again and saved. 30:19 18:16 RESERVED RX_TRL_PHY_ID Receive timing reference physical link ID. This is translated from the TRL_LID field in the incoming ICP cells, then used to control Rx IDCC TSB The TRL LID info captured from incoming ICP cells. Indicates whether a adjust_delay procedure is current active. Adjust delay could be started by PM command adjust_delay, or internally by LASR procedure. `0': No delay adjustment is in progress. `1': Delay adjustment is in progress. 6 DELAY_ADJUST_ RDAT_TOGGLE The last value of the delay_toggle bit read from RDAT group context memory. A transition on this bit is used to determine the ongoing adjust_delay process is finished. Indicates whether the current adjust_delay process is started by PM. `0': the adjust-delay is started internally by LASR. `1' the adjust-delay is started by PM. 4:0 RESERVED
15:13 12:8 7
RESERVED RX_TRL_LID DELAY_ADJUST_ ACTIVE
5
DELAY_ADJUST_I S_PM
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10:15
31:0
RESERVED
RIPP TX Link Context Record Memory Area The TX link context record area is located in the RIPP context memory. There are 8 TX link context records that contain the current state machine states and status information for the corresponding TX links. Each record is 2 words deep by 32 bits wide, and is addressed by the physical link number. MEM_ADDR = Area_base_address + physical link number * 0x2 + Word Offset Unless otherwise specified, all the data fields and the reserved fields should be cleared (to all `0's) by PM prior to adding the link, and will be internally cleared by RIPP during a group-restart. Table 13 WORD 0 RIPP TX Link Context Record Structure BIT 31 DATA FIELD TX_LINK_EN DESCRIPTION Flag bit indicating whether the link is enabled or not. "0": not enabled, link in UNASSIGNED state "1: enabled. This field is set by RIPP during add_link or add_group command processing. It is cleared by RIPP upon finishing deleting the link. It may be polled by PM to determine the progress of link addition or deletion. This field will remain at its current value during a group-restart. 30:27 TX_LSM TX Link state machine state. "0000": DELETED(NOT_IN_GROUP) "0010": UNUSABLE "1100": USABLE "1110": ACTIVE
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Others: reserved This field is cleared by PM during link record initialization. 26:16 15 RESERVED TX_LINK_TIMER_E N TX link timer enable. The enable bit is set when the timer is loaded; it is cleared when either a timeout occurs or the timer is disabled. TX link timer. Implemented as 4-bit down counter. The counter is loaded with the appropriate timeout value when the timer is enabled, and decrements on every timer tick, until it reaches zero. A timeout event is declared when a timer tick occurs and the counter equals zero, if the timer is enabled. Far end RX LSM state for the link. This is copied from the appropriate TX LSM state field in the incoming ICP cells. This field indicates the link has been considered unusable by PM. This bit is set up on PM issuing UNUSABLE_LINK command, and cleared up on PM issuing RECOVER_LINK command. This field is programmed by PM during link record initialization. This field will remain at its current value during a group-restart. 2:0 TX_LINK_PM_UNU SABLE_CAUSE Cause specified by PM for the link to be unusable. This field is used by RIPP to notify FE.
14:12 11:8
RESERVED TX_LINK_TIMER
7 6:4
RESERVED FE_RX_LSM
3
TX_LINK_PM_UNU SABLE
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"000": No cause specified "010": Fault. "011": Mis-connected "100": Inhibited "100": Failed Others: Reserved (currently considered the same as no cause specified). This field is programmed by PM during link record initialization. This field will remain at its current value during a group-restart. 1 31:10 9:8 RESERVED FE_RX_DEFECT Defect status reported in last receive ICP cell. 00) No defect 01) Physical Link Defect (e.g. LOS, OOF/LOF, LCD) 10) LIF 7:5 4 TX_ACTIVE_INT 11) LODS Reserved Indicates that the NE TX LSM transitioned into/out of Active state. This bit is reset immediately after the read_event command is executed for the group of which this link is a member. FE_RX_UNUSABLE Indicates that FE RX LSM transitioned into/out of UNUSABLE state. _INT This bit is reset immediately after read_event command is executed for the group of which this link is a member. Indicates that the FE RX Defect FE_RX_DEFECT_I
3
2
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NT
indication changed. This bit is reset immediately after read_event command is executed for the group of which this link is a member. Indicates the LASR procedure timed out prior to the link entering the ACTIVE state. This bit is reset immediately after read_event command is executed for the group of which this link is a member.
1
TX_TIMEOUT_INT
0
RESERVED
RIPP RX Link Context Record Memory Area The RX link context record area is located in the RIPP context memory. There are 8 RX link context records that contain the current state machine states and status information for the corresponding RX links. Each record is 2 words deep by 32 bits wide, and is addressed by the physical link number. MEM_ADDR = Area_base_address + physical link number * 0x2 + Word Offset Unless otherwise specified, all the data fields and the reserved fields should be cleared (to all `0's) by PM prior to adding the link, and internally cleared by RIPP during group restart. Table 14 RIPP RX Link Context Record structure DATA FIELD RX_LINK_EN DESCRIPTION Flag bit indicating if the link is enabled or not. "0": not enabled, link in UNASSIGNED state. "1: enabled. This field is set by RIPP during add_link or add_group command processing. It is cleared by RIPP upon
WORD BIT 0 31
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finishing deleting the link. It may be polled by PM to determine the progress of link addition or deletion. This field will remain at its current value during a group-restart. 30:25 RX_LSM RX Link state machine state. "000000": START_UP, No M has been negotiated yet. "000010": DELETED, waiting for FE "00010"0: DELETED, waiting for DCB underrun "000110": UNUSABLE_NO_LID (report to FE as not_in_group) "001000": UNUSABLE "001010": UNUSABLE, waiting for DCB underrun "001100": Blocking, waiting for FE "110000": USABLE "110010": USABLE, waiting for data in DCB to be played out, reporting USABLE. "110011": USABLE, waiting for FE "110100": ACTIVE, waiting for RX cell reader to become active, reporting USABLE. "110110": ACTIVE, waiting for the global synchronization event to report ACTIVE to the FE. "111000: ACTIVE, reporting ACTIVE Others: reserved This field is cleared (UNASSIGNED state) by PM during link record initialization. 24 reserved
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23
RX_LID_VALID
Flag bit indicating if the value in the RX_LID field is valid or not. "0": invalid "1: valid. This field is cleared by PM during link record initialization. It will be set by RIPP upon the success of RDAT LID validation.
22:21 20:16
RESERVED RX_LID LID value for the RX physical link. This field is cleared by PM during link record initialization. It will be set by RIPP upon the success of RDAT LID validation.
15
RX_LINK_TIMER_ EN
RX link timer enable. The enable bit is set when the timer is loaded; it is cleared when either a timeout occurs or the timer is disabled. RX link timer. Implemented as 4-bit down counter. The counter is loaded with the appropriate timeout value when the timer is enabled, and decrements on every timer tick, until it reaches zero. A timeout event is declared when a timer tick occurs and the counter equals zero, if the timer is enabled. Far end TX LSM state for the link. This is copied from the appropriate TX LSM state field in the incoming ICP cells. This field indicates the link has been considered unusable by PM. This bit is set up on PM issuing UNUSABLE_LINK command, and
14:12 11:8
RESERVED RX_LINK_TIMER
7 6:4
RESERVED FE_TX_LSM
3
RX_LINK_PM_UN USABLE
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cleared upon PM issuing RECOVER_LINK command. This field is programmed by PM during link record initialization. This field will remain at its current value during a group-restart. 2:0 RX_LINK_PM_UN USABLE_CAUSE Cause specified by PM for the link to be unusable. This field is used by RIPP to notify FE. "000": No cause specified "010": Fault. "011": Mis-connected "100": Inhibited "100": Failed Others: Reserved (currently considered the same as no cause specified). This field is programmed by PM during link record initialization. This field will remain at its current value during a group-restart. 1 31:21 20 19 RESERVED LINK_DELAY_GO OD LODS_OVR The result of the last differential delay evaluation for the link. LODS, DCB overrun. Indicates that the DCB buffer is in an overrun condition. This occurs when the transport delay for the link is detected to be outside the programmed limit and the transport delay is longer than the other links within the group. LODS, DCB under-run. Indicates that the DCB buffer is in an underrun condition. LCD, Loss of Cell Delineation Defect is
18
LODS_UNDERRU N LCD
17
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present on this link. 16 15:11 10 LIF RESERVED RX_ACTIVE_INT RX LSM transition into/out of Active state. This bit is reset immediately after read_event command is executed for the group of which this link is a member. 9 IDLE_CELL_INT Physical layer idle cells were received on the RX link. This bit is reset immediately after read_event command is executed for the group of which this link is a member. 8 FE_TX_UNUSABL E_INT FE TX LSM transitioned into or out of the UNUSABLE state. This bit is reset immediately after the read_event command is executed for the group of which this link is a member. 7 DIFF_DELAY_INT Differential Delay is out of bounds on link addition/or recovery. This indicates the delay on the link was out of bounds of the programmed differential delay and the link failed to come up for this reason. This bit is reset immediately after the read_event command is executed for the group of which this link is a member. 6 LODS_OVERRUN_ LODS, DCB overrun. An overrun INT condition occurred. This bit is reset immediately after read_event command is executed for LIF, A loss of IMA Frame defect condition is present on this link.
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the group of which this link is a member. 5 LODS_UNDERRU N_INT LODS, DCB underrun. Indicates that the DCB buffer experienced an underrun condition and has disabled itself from forwarding traffic to the ATM layer. An underrun occurs when the transport delay for the link is detected to be outside the programmed limit and the transport delay is smaller than the other links within the group In general, this will happen only if the transport delay of the link changes. An underrun condition requires that the link delay be revalidated prior to being placed back in service. This bit is reset immediately after the read_event command is executed for the group of which this link is a member. 4 LCD_INT A change of state of the LCD status bit was detected. This bit is reset immediately after read_event command is executed for the group of which this link is a member. 3 LIF_INT A change of state of the LIF status bit was detected. This bit is reset immediately after read_event command is executed for the group of which this link is a member. 2 INVALID_ICP _INT Invalid ICP parameters detected on RX link during validation of the ICP cell parameters causing validation to fail. Possible reasons include: Invalid LID (i.e., duplicate).
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Invalid ICP cell offset (out of range). Invalid RX IMA ID, which may indicate a misconnectivity problem. Invalid OAM label received after IMA version being determined through negotiation. Invalid Group symmetry received after symmetry being determined through negotiation. This bit is reset immediately after read_event command is executed for the group of which this link is a member. 1 RX_TIMEOUT_INT Indicates the LASR procedure timed out prior to the link entering the ACTIVE state. This bit is reset immediately after the read_event command is executed for the group of which this link is a member. 0 INVALID_FE_TX_I NT Invalid FE TX LSM states were detected in a incoming non-errored ICP cell. This bit is reset immediately after the read_event command is executed for the group of which this link is a member.
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Register 0x20C: RIPP Timer Tick Configuration Register Bit 15:0 Type R/W Function Timer_tick_interval Default 0x3473
Timer-tick_interval This value controls the interval between timer tick events. The timer ticks are internally generated by counting sysclk pulses. The count of sysclk pulses between sysclk pulsesis a 26 bit integer, the most significant 16 bits of which are specified here, and the lower 10-bits are set to `0's internally. To give an example, a Timer_tick_interval value of 0 x 3473 represents a value of 0XD1CC00 (13,749,248 decimal) sysclk pulses; this translates to about 275 milliseconds in real time assuming a 50 MHz sysclk.
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Register 0x20E: Group Timeout Register # 1 Bit 15:12 11:8 7:4 3:0 Type R/W R/W R/W R/W Function Group_startup_ack_timeout Group_config_abort_timeout RX_usable_timeout RX_active_timeout Default 0x4 0x4 0x4 0x4
This register holds the time-out values used at different states of the group state machine or the group-wide procedures (such as group start-up and LASR). The actual time represented by the timeout value in this register can be obtained as: Real_time = Timeout_value * Internal_timer_tick_interval Group_config_abort_timeout: The timeout value determines how long the GSM should stay in Config_Aborted state before it can move back to Start-up state, if no new parameters are proposed by the FE and PM does not issue a restart_group command. Group_startup_ack_timeout: The timeout value determines how long the GSM should stay in Start-up-Ack state before it can move back to Start-up state, if the FE GSM is not in one of the following states: Start-up-Ack, Insufficient-Links, Blocked, or Operational. RX_usable_timeout: During the group start-up or LASR, this timeout value determines how long the RIPP should wait before it can move any RX LSMs to Usable state (unless all the RX links involved are out of defect status). In the case of group start-up, the timer is started when the GSM enters Insufficient-links state; during LASR, it is started when the PM issues add_link command. RX_active_timeout: During the group start-up or LASR, this timeout value determines how long the RIPP should wait before it can move any RX LSMs to Active state (unless all the links involved are being reported TX = Usable by the FE). The timer is started after the RX = usable synchronization point.
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Register 0x210: Group Timeout Register # 2 Bit 15:4 3:0 R/W Type Function Reserved TX_active_timeout 0x4 Default
This register holds additional group time-out values. TX_active_timeout: During the group start-up or LASR, this value determines how long the RIPP should wait before it can move any TX LSMs to Active state (unless all the links involved are being reported RX = Usable by the FE). In the case of group start-up, the timer is started when the GSM enters Insufficient-links state; during LASR, it is started when the PM issues add_link command.
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Register 0x212: TX Link Timeout Register Bit 15:4 3:0 Type R/W R/W Function Reserved TX_link_deleted_timeout Default 0 0x4
This register holds the time-out values used at different states of the TX LSM. The actual time represented by the timeout value in this register can be obtained as: Real_time = Timeout_value * Internal_timer_tick_interval TX_link_deleted_timeout: During link deletion, this value determines how long the TX LSM should stay in the DELETED state before it can move to the UNASSIGNED state (if the FE does not report RX != Active).
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Register 0x214: RX Link Timeout Register Bit 15:8 7:4 3:0 Type R/W R/W R/w Function Reserved RX_link_blocked_timeout RX_link_deleted_timeout Default 0 0x4 0x4
This register holds additional time-out values used at different states of the RX LSM. The actual time represented by the timeout value in this register can be obtained as: Real_time = Timeout_value * Internal_timer_tick_interval RX_link_deleted_timeout: In the case of link deletion, this value determines how long the RX LSM should stay in the DELETED state before it can move to the UNASSIGNED state (if the FE does not report TX != Active). RX_link_blocked_timeout: In the case of link inhibiting, this value determines how long the RX LSM should stay in the BLOCKED state before it can move to the UNUSABLE state (if the FE does not report TX != Active).
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Register 0x216: RIPP Interrupt status Register Bit 15 14 13:2 1:0 RO Type RO RO Function FIFO_BUSY FIFO_NOT_EMPTY Reserved Group tag 0 Default 0 0
This register serves as the read interface to the internal PM message FIFO. Each ECBI read to the register will cause a read to the FIFO, which means the register content will be automatically updated. Group_tag: This is the group tag value of the group that generated the event. This field is only valid if FIFO_NOT_EMPTY is set and FIFO_BUSY is not set. FIFO_NOT_EMPTY The current PM message FIFO status. A logic high means the FIFO is not empty; a logic low means the FIFO is empty. This bit is only valid if FIFO_BUSY is not set. FIFO_BUSY Indicates that the FIFO is in the process of retrieving the next entry. The Busy bit will usually be cleared within 4 sysclk cycles from the end of a read.
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Register 0x218:RIPP Group Interrupt Enable Register Bit 15:10 9 8 7 6 5 4 3 2 1 0 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Function Reserved PM_ADJUST_DELAY_DO NE_INT_EN INVALID_TRL_INT_EN GRP_TIMING_INT_EN FE_TIMEOUT_INT_EN GR_TIMEOUT_INT_EN FE_ABORT_INT_EN NE_ABORT_INT_EN GTSM_INT_EN FE_GSM_INT_EN NE_GSM_INT_EN Default 0 0 0 0 0 0 0 0 0 0 0
The above enable bits provides a global enable for the corresponding IMA group interrupts. If an interrupt enable bit is not set, the respective interrupt is disabled for all groups. If a bit is set, the individual group interrupt enable is used. 0 - Disable group interrupt for all links. 1- Use individual group interrupt enable.
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Register 0x21A:RIPP TX Link Interrupt Enable Register Bit 15:5 4 3 2 1 0 Type R/W R/W R/W R/W R/W R/W Function RESERVED TX_ACTIVE_INT_EN FE_RX_UNUSABLE_INT_ EN FE_RX_DEFECT_INT_EN TX_TIMEOUT_INT_EN UNUSED Default 1
The above enable bits provides a global enable for the corresponding TX link interrupts. If an interrupt enable bit is not set, the respective interrupt is disabled for all links. If a bit is set, the individual Tx Link Interrupt enable is used. 0 - Disable corresponding Tx Link interrupt for all links. 1 - Use individual corresponding Tx Link interrupt enable.
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Register 0x21C:RIPP RX Link Interrupt Enable Register Bit 15:11 10 9 8 7 6 5 4 3 2 1 0 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Function RESERVED RX_ACTIVE_INT_EN IDLE_CELL_INT_EN FE_TX_UNUSABLE_INT_ EN DIFF_DELAY_INT_EN LODS_OVERRUN_INT_E N LODS_UNDERRUN_INT_ EN LCD_INT_EN LIF_INT_EN INVALID_ICP_INT_EN RX_TIMEOUT_INT_EN UNUSED Default 0 0 0 0 0 0 0 0 0 0 0 0
The above enable bits provide a global enable for the corresponding Rx link interrupts. If an interrupt enable bit is not set, the respective interrupt is disabled for all links. If a bit is set, the individual Rx Link Interrupt enable is used. 0 - Disable group link interrupt for all links. 1 - Use individual link interrupt enable for each link.
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Register 0x220-22C: RIPP Command Register Address 0x220 Bit 15 14:10 9 8 7:0 0X222 0X224 0X226 0X228 0X22A 0X22C 15:0 15:0 15:0 15:0 15:0 15:0 R/W R/W R/W R/W R/W R/W R/W Type R/W R/W R/W Function CMD_BUSY CMD_CODE CMD_ACK Reserved CMD_WR_DATA00 CMD_WR_DATA01_LSB CMD_WR_DATA01_MSB CMD_WR_DATA02_LSB CMD_WR_DATA02_MSB CMD_WR_DATA03_LSB CMD_WR_DATA03_MSB 0 0 0 0 0 0 0 Default 0 0 0
These array registers control the issuing of PM commands. Writing to the first location in the array (0x30) causes a new command to be issued to RIPP. The command operands are carried in the rest of the registers. CMD_ACK: This bit indicates whether a command has been accepted (logic high) or rejected (logic low) by RIPP. It is updated by RIPP before the CMD_BUSY is cleared. CMD_CODE: This is set by the microprocessor to indicate which command is being issued. See Table 15 Command Register Encoding for the details. CMD_BUSY: This bit is set to `1' internally upon detecting a microprocessor write to this register location; the write indicates that a new command is being issued. After the command is accepted by RIPP, RIPP clears the bit to `0' asynchronously to indicate that it is now ready to take the next command. RIPP will also update the CMD_ACK bit to indicate whether the command has
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been accepted; it puts the return data - if there is any - in the command-read data registers. CMD_WR_DATA00: 8-bit field used to carry the first operand of the current command. See Table 15 Command Register Encoding for the details. CMD_WR_DATA01 - CMD_WR_DATA03: 32-bit data fields used to carry the rest of the operands of the current command. See Table 15 Command Register Encoding for the details. Table 15 Command Add_group Command Register Encoding Cmd_cod e 00000 Cmd_wr_data Cmd_wr_data01 through 00 cmd_wr_data03 Group_tag Cmd_data01: TX_PHY_VALID vector Cmd_data02: RX_PHY_VALID vector The rest: Don't care Delete_grou 00001 p Restart_gro up Inhibit_grou p Not_inhibit_ group Start_LASR 00010 00100 00101 01000 Group_tag Group_tag Group_tag Group_tag Group_tag Don't care. Don't care. Don't care. Don't care. Cmd_data01: TX_LINK_VEC Cmd_data02: RX_LINK_VEC The rest: Don't care. Delete_link 01001 Group_tag Cmd_data01: TX_LINK_VEC Cmd_data02: RX_LINK_VEC The rest: Don't care. Set_rx_phy
01010 Group_tag
Cmd_data02: RX_LINK_VEC
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_defect
Cmd_data03: Bit 0: rx link physical defect status (LOS, LOF, AIS): `0': no defect `1': defect exists and need to be reported to FE The reset: Don't care.
Unusable_li nk
01100
Group_tag
Cmd_data01: TX_LINK_VEC Cmd_data02: RX_LINK_VEC Cmd_data03: Bit 6:4: TX_CAUSE. Encoding: "001": No cause specified "010": Fault. "011": Mis-connected "100": Inhibited "100": Failed Others: Reserved (no effect, command void) Bit 2:0: RX_CAUSE. "001": No cause specified "010": Fault. "011": Mis-connected "100": Inhibited "100": Failed The reset: Don't care.
Update_test 10000 _ptn
Group_tag
Cmd_data01: Bit 13: test pattern active indication Bit 12:8: LID value of the TX Link to be tested. Bit 7:0: Tx test pattern
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The rest: Don't care. Update_tx_t 10001 rl Group_tag Cmd_data01: Bit 4:0: LID value of the TX Link to be used as the new TRL. The rest: Don't care. Read_event 11000 Read_delay Adjust_dela y 11001
11010
Group_tag Group_tag
Group_tag
Don't Care. Don't Care.
Cmd_data01: Bit15 : DELAY_ADJUST_MODE `0': Remove delay
`1': Add delay
Bit 9:0: Indicates the amount of delay
to be added to/removed from a Group.
The rest: Don't care.
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Register 0x22E: Command Read Data Control Register Bit 15:2 1:0 R/W Type Function Reserved Cmd_read_data_page_ sel Default 0 0
CMD_READ_DATA_PAGE_SEL Selects which page in the command read data register array is to be made available in the Command Read Data Register Array. A logic `0' selects page 0, while a logic `1' selects page 1 and a logic `2' selects page 2. The pages may be changed at anytime to enable access to the complete information provided by the read event command. See "Register 0x240-0x029E" for details of the contents of the pages.
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Register 0x230: ICP Cell Forwarding Status Register Bit 15:1 0 Type R/W R/W Function Reserved PM_ICP_AVL Default 0 0
This register serves as the current PM_ICP_AVL interrupt status. PM_ICP_AVL: This bit is set by the RIPP state machine to indicate that there has been a new ICP cell copied over to the ICP cell buffer register area. It is cleared upon the microprocessor reading this register location.
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Register 0x232: ICP Cell Forwarding Control Register Bit 15:2 1 0 R/W R Type Function Reserved ICP_FWD_LOCK_REQ ICP_FWD_LOCK_GRANT 0 Default 0
ICP_FWD_LOCK_GRANT: This bit serves as an access lock bit controlling the access to the forwarding ICP buffer. A read from this location returns the current lock status. When the lock bit is set to `1', the microprocessor is granted read access to the buffer; further writes by the RIPP internal logic are prohibited. Otherwise RIPP has control over the area. ICP_FWD_LOCK_REQ: Writing `1' to the register location requests the lock for microprocessor read access; while writing `0' releases the lock.
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Register 0x240- 0x29E:RIPP Command Data Register Array Address 0x240 0x242 0x244 0x246 0x248 0x24A 0x24C 0x24E 0x250 0x252 0x254 0x256 0x258 0x25A 0x25C 0x25E 0x260 0x262 0x264 0x266 0x268 0x26A 0x26C 0x26E 0x270 Bit 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 Type R R R R R R R R R R R R R R R R R R R R R R R R R Function CMD_DATA00_LSB CMD_DATA00_MSB CMD_DATA01_LSB CMD_DATA01_MSB CMD_DATA02_LSB CMD_DATA02_MSB CMD_DATA03_LSB CMD_DATA03_MSB CMD_DATA04_LSB CMD_DATA04_MSB CMD_DATA05_LSB CMD_DATA05_MSB CMD_DATA06_LSB CMD_DATA06_MSB CMD_DATA07_LSB CMD_DATA07_MSB CMD_DATA08_LSB CMD_DATA08_MSB CMD_DATA09_LSB CMD_DATA09_MSB CMD_DATA0A_LSB CMD_DATA0A_MSB CMD_DATA0B_LSB CMD_DATA0B_MSB CMD_DATA0C_LSB Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Address 0x272 0x274 0x276 0x278 0x27A 0x27C 0x27E 0x280 0x282 0x284 0x286 0x288 0x28A 0x28C 0x28E 0x290 0x292 0x294 0x296 0x298 0x29A 0x29C 0x29E 0x2A0 0x2A2 0x2A4 0x2A6
Bit 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0
Type R R R R R R R R R R R R R R R R R R R R R R R R R R R
Function CMD_DATA0C_MSB CMD_DATA0D_LSB CMD_DATA0D_MSB CMD_DATA0E_LSB CMD_DATA0E_MSB CMD_DATA0F_LSB CMD_DATA0F_MSB CMD_DATA10_LSB CMD_DATA10_MSB CMD_DATA11_LSB CMD_DATA11_MSB CMD_DATA12_LSB CMD_DATA12_MSB CMD_DATA13_LSB CMD_DATA13_MSB CMD_DATA14_LSB CMD_DATA14_MSB CMD_DATA15_LSB CMD_DATA15_MSB CMD_DATA16_LSB CMD_DATA16_MSB CMD_DATA17_LSB CMD_DATA17_MSB CMD_DATA18_LSB CMD_DATA18_MSB CMD_DATA19_LSB CMD_DATA19_MSB
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Address 0x2A8 0x2AA 0x2AC 0x2AE 0x2B0 0x2B2 0x2B4 0x2B6 0x2B8 0x2BA 0x2BC 0x2BE
Bit 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0
Type R R R R R R R R R R R R
Function CMD_DATA1A_LSB CMD_DATA1A_MSB CMD_DATA1B_LSB CMD_DATA1B_MSB CMD_DATA1C_LSB CMD_DATA1C_MSB CMD_DATA1D_LSB CMD_DATA1D_MSB CMD_DATA1E_LSB CMD_DATA1E_MSB CMD_DATA1F_LSB CMD_DATA1F_MSB
Default 0 0 0 0 0 0 0 0 0 0 0 0
The 64 registers in address range 0x240-0x29E serve as a data bank organized as three pages, each with 32 32-bit words. Those registers are used to hold the return value from the command. The value of cmd_read_data_page_select determines which page is currently accessible. See Table 16 for the details. Table 16
Command
Command data register array format
Cmd_data01 through cmd_data18
Read_event
Cmd_rd_data n (n = 0, .... 31):, page 0: Group interrupt/status status page. Where Cmd_rd_data0: 32 bit vector where every bit corresponding to a tx link. A logic `0' means there is not interrupt condition on the link, while a logic `1' means interrupt condition exists on the link. Cmd_rd_data1: 32 bit vector where every bit corresponding to a rx link. There a 32 entries,
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one for each possible link in the IMA group. A logic `0' means there is not interrupt condition on the link, while a logic `1' means interrupt condition exists on the link. Cmd_rd_data2: group interrupt/status. There are 32 entries, one for each possible link in the IMA group. See Table 17 for detail of the bits Page 1: Link Interrupt Status page. See Table 18 for details of the bits. Page 2: Link Status Page. See Table 19 for details of the bits. Note that the TX/RX links here are sorted in the same order as in the TX_PHY_VALID and RX_PHY_VALID vectors. Read_delay Cmd_rd_data n (n = 0, .... 31), page 0: Bit 18: Current overrun defect status Bit 16: Current LCD defect status. Bit 17: Current LIF defect status. Bit 15:0: rx link write pointers for the n-th RX link. Note that the TX/RX links here are sorted in the same order as in the TX_PHY_VALID and RX_PHY_VALID vectors. Cmd_rd_data 0, page 1: Bit 15:0: rx group read pointer Cmd_rd_data 1, page 1: Bit 31:0: Current RDAT reader active vector for the group. If none of the links are active (i.e., all 32 bits are zeros), the read pointer should be considered as invalid. Table 17 Word Bit 31:26 Group Error/Status Bit Mapping Data Field RESERVED Description Reserved
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Word Group Interrupts (10 bit)
Bit 25
Data Field PM_ADJUST_DELA Y_DONE_INT
Description PM adjust_delay procedure done. This means an adjust_delay procedure invoked by the PM command is successfully finished or aborted. Invalid RX TRL. This means the FE specified a not-in-group link to be the TRL. Group timing mismatch. This means the FE IMA transmit clock mode does not mach the NE transmit clock mode. Startup-Ack Timeout. The FE fails to transition into the STARTUP-ACK state prior to the NE timing out.
24
FE_TRL_INT
23
GROUP_TIMING_IN T FE_TIMEOU_INT
22
21
GROUP_TIMEOUT_I GSM fails to come out of an NT insufficient-links state during a group start-up procedure before the relevant timer expires. FE_ABORT_INT NE_ABORT_INT FE entered CONFIG-ABORTED state during group start-up. Entered NE Config aborted state, FE group parameters unacceptable during group start-up. Possible causes are: IMA OAM label proposed by FE not acceptable. Group symmetry proposed by FE not acceptable. RX M proposed by FE not acceptable
20 19
18
GTSM_INT
GTSM state change.
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Word
Bit 17 16
Data Field FE_GSM_INT NE_GSM_INT RESERVED
Description FE GSM state change. NE GSM state change. Reserved
Group Status (10 bit)
15:11
10
FE_TRL_STATUS
Invalid RX TRL. This means the FE specified a not-in-group link to be the TRL. Group timing mismatch GTSM state FE GSM state: Group state machine state. "0000": Start-up "0001": Start-up-ACK "0010": Config-Aborted - Unsupported M "0011": Config-Aborted - Incompatible group symmetry "0100": Config-Aborted - Unsupported IMA versions "0101": Reserved "0110": Reserved "0111": Config-Aborted - Other reasons "1000": Insufficient-links "1001": Blocked "1010": Operational "1011"-"1111" Reserved
9 8 7:4
GROUP_TIMING_MI SMATCH GTSM FE_GSM
3:0
NE_GSM
NE GSM state
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Table 18 Word RX Link Error Status (12 bit) Bit
Link Event Interrupt Bit Mapping Data Field Description Reserved
31:27
26 25 24
RX_ACTIVE_INT IDLE_CELL_INT FE_TX_UNUSABLE _INT
RX LSM transition into/out of Active state. Physical layer idle cells were received on the RX link. FE TX LSM transitioned into or out of the UNUSABLE state.
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Word
Bit 23
Data Field DIFF_DELAY_INT
Description Differential Delay is out of bounds on link addition/or recovery. This indicates the delay on the link was out of bounds of the programmed differential delay and that the link failed to come up for this reason. LODS, DCB overrun. An overrun condition occurred.
22 21
LODS_OVERRUN_I NT
LODS_UNDERRUN_ LODS, DCB underrun. Indicates that INT the DCB buffer experienced an underrun condition and has disabled itself from forwarding traffic to the ATM layer. An underrun occurs when the transport delay for the link is detected to be outside the programmed limit and the transport delay is smaller than the other links within the group In general, this will happen only if the transport delay of the link changes. An underrun condition requires that the link delay be revalidated prior to being placed back in service. LCD_INT LIF_INT INVALID_ICP _INT A change of state of the LCD status bit was detected. A change of state of the LIF status bit was detected. Invalid ICP parameters detected on RX link during validation of the ICP cell parameters causing validation to fail. Possible reasons include: Invalid LID (i.e., a duplicate). Invalid ICP cell offset (out of range). Invalid RX IMA ID, which may indicate a misconnectivity problem. Invalid OAM label received after IMA
20 19 18
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Word
Bit
Data Field
Description version was determined through negotiation. Invalid Group symmetry received after symmetry was determined through negotiation.
17
RX_TIMEOUT_INT
Indicates the LASR procedure timed out prior to the link entering the ACTIVE state. Reserved Reserved
16 TX Link Error Status (8 bit) 15:5
RESERVED RESERVED
4 3 2 1
TX_ACTIVE_INT FE_RX_UNUSABLE _INT FE_RX_DEFECT_IN T TX_TIMEOUT_INT
Indicates that the NE TX LSM transitioned into/out of Active state. Indicates that FE RX LSM transitioned into/out of UNUSABLE state. Indicates that the FE RX Defect indication changed. Indicates the LASR procedure timed out prior to the link entering the ACTIVE state. Reserved
0 Table 19 Word RX Link Error Status (15 bit) Bit 31
RESERVED Link Status Bit Mapping Data Field DATA_PLAYOUT
Description Reserved
30
LODS_OVR
LODS, DCB overrun indicated by RDAT.
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Word
Bit 29
Data Field LODS_UNDERRUN
Description LODS, DCB under-run indicated by RDAT.
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Word
Bit 28 27 26:24
Data Field LCD LIF FE_TX_LSM
Description LCD, indicated by RDAT. LIF, indicated by RDAT. FE Tx LSM state "000": Not in Group "001": UNUSABLE "010": UNUSABLE (Fault) "011": UNUSABLE (Mis-connected) "100" :UNUSABLE (Inhibited) "101": UNUSABLE (Failed) "110": USABLE "111": ACTIVE
23:21 20:16 TX Link Error Status (8 bit) 15:8
RX_LSM_ICP RX_LID
NE Rx LSM state. Rx LID Reserved
7:6 5:3 2:0
FE_RX_DEFECT FE_RX_LSM TX_LSM_ICP
FE Rx Defect FE Rx LSM state NE Tx LSM state.
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Register 0x2C0- 0x2FE: Forwarding ICP Cell Buffer Address 0x2C0 0x2C2 0x2C4 0x2C6 0x2C8 0x2CA 0x2CC 0x2CE 0x2D0 0x2D2 0x2D4 0x2D6 0x2D8 0x2DA 0x2DC 0x2DE 0x2E0 0x2E2 0x2E4 0x2E6 0x2E8 0x2EA 0x2EC 0x2EE 0x2F0 Bit 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 Type R R R R R R R R R R R R R R R R R R R R R R R R R Function ICP_WORD00_LSB ICP_WORD00_MSB ICP_WORD01_LSB ICP_WORD01_MSB ICP_WORD02_LSB ICP_WORD02_MSB ICP_WORD03_LSB ICP_WORD03_MSB ICP_WORD04_LSB ICP_WORD04_MSB ICP_WORD05_LSB ICP_WORD05_MSB ICP_WORD06_LSB ICP_WORD06_MSB ICP_WORD07_LSB ICP_WORD07_MSB ICP_WORD08_LSB ICP_WORD08_MSB ICP_WORD09_LSB ICP_WORD09_MSB ICP_WORD0A_LSB ICP_WORD0A_MSB ICP_WORD0B_LSB ICP_WORD0B_MSB ICP_WORD0C_LSB Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Address 0x2F2 0x2F4 0x2D6 0x2F8 0x2FA 0x2FC 0x2FE
Bit 15:0 15:0 15:0 15:0 15:0 15:0 15:0
Type R R R R R R R
Function ICP_WORD0C_MSB ICP_WORD0D_LSB ICP_WORD0D_MSB ICP_WORD0E_LSB ICP_WORD0E_MSB ICP_WORD0F_LSB ICP_WORD0F_MSB
Default 0 0 0 0 0 0 0
The 32 registers in the address range 0x2A0-0x2DE serve as a data bank organized as 16 32-bit words. Those words are used to store the ICP cell forwarded to PM. See Table 20 for the details the format. Table 20 Receive ICP Cell Buffer Structure Description Octets 6-53 of the payload contained in the last non-errored ICP cell for this link. 31:24 0 1 2 3 4 5 6 7 8 9 10 11 Octet 6 Octet 10 Octet 14 Octet 18 Octet 22 Octet 26 Octet 30 Octet 34 Octet 38 Octet 42 Octet 46 Octet 50 23:16 Octet 7 Octet 11 Octet 15 Octet 19 Octet 23 Octet 27 Octet 31 Octet 35 Octet 39 Octet 43 Octet 47 Octet 51 15:8 Octet 8 Octet 12 Octet 16 Octet 20 Octet 24 Octet 28 Octet 32 Octet 36 Octet 40 Octet 44 Octet 48 Octet 52 7:0 Octet 9 Octet 13 Octet 17 Octet 21 Octet 25 Octet 29 Octet 33 Octet 37 Octet 41 Octet 45 Octet 49 Octet 53
Word Bits Parameter icp_data
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Word Bits Parameter 12 31:1 0 9
Description Reserved.
position_error The current ICP cell was received in an unexpected position within the IMA frame. If the contents of the cell are valid, then the ICP cell is considered valid, but the IFSM will transition to the IMA Hunt state. header_invali The ATM cell header is not a correct ICP cell d header. cid_invalid label_invalid lid_mm ima_id_mm m_mm seq_error The Cell ID does not indicate the OAM Cell Type is ICP. The OAM Label does not indication IMA version 1.1. The link identifier in the current ICP cell does not match the LID in validation memory. The IMA ID in the current ICP cell does not match the IMA ID in validation memory. The IMA Frame Length in the current ICP cell does not match the length in validation memory. The IMA Frame Sequence Number in the current ICP cell does not match the sequence number maintained by the RDAT. The ICP Cell Offset in the current ICP cell does not match the offset in validation memory. The link stuff indication in the current ICP cell has not progressed properly from the previous value. Reserved.
8 7 6 5 4 3 2
1 0 13:15 .
icp_offset_m m stuff_invalid
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11.8 RDAT Registers Register 0x300: RDAT Indirect Memory Command Bit 15 14 13:4 3:0 R/W Type RO R/W Function MEM_BUSY MEM_RWB Unused MEM_SELECT Default 0 0 0 0
Writing to this register triggers an indirect memory access to the RDAT tables. The indirect memory address (and data register for write operations) must be configured prior to writing the register. MEM_SELECT: The indirect memory select indicates the memory table within the RDAT which will be accessed. MEM_SE LECT 0x00 0x01 0x02 0x03 0x04 0x05 RDAT Memory Table RDAT Link Statistics Memory RDAT IMA Group Statistics Memory RDAT TC Link Statistics Memory RDAT Validation Memory RDAT Link Context Memory RDAT Link Sequence Memory Receive ICP Cell Buffer RDAT IMA Group Context Memory Address Range 0x000-0x01F 0x000-0x007 0x000-0x00F 0x000-0x00F 0x000-0x00F 0x000-0x007
0x06-0x07 Reserved 0x08 0x09 0x000-0x07F 0x000-0x007
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MEM_SE LECT 0x0A 0x0B0x0C 0x0D 0x0E0x0F MEM_RWB:
RDAT Memory Table RDAT TC Context Memory Reserved Receive ATM Congestion Count Register Reserved
Address Range 0x000-0x007
N/A
The memory indirect access control bit (MEM_RWB) selects between a configure (write) or interrogate (read) access to the RDAT internal memory. Writing a logic 0 to MEM_RWB triggers an indirect write operation. Data to be written is taken from the Indirect Memory Data registers. Writing a logic 1 to MEM_RWB triggers an indirect read operation. The read data can be found in the Indirect Memory Data registers. The address within a memory table can be found in the Indirect Memory Address register. MEM_BUSY: The indirect memory access status bit (MEM_BUSY) reports the progress of an indirect access A write to the Indirect Memory Command register triggers an indirect access and sets the MEM_BUSY bit to a logic 1, MEM_BUSY will remain logic 1 until the access is complete. This register should be polled to determine either: (1) when data from an indirect read operation is available in the Indirect Memory Data registers or (2) when a new indirect write operation may commence.
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Register 0x302: RDAT Indirect Memory Address Bit 15:11 10:0 R/W Type Function Unused MEM_ADDR Default 0 0
This register should not be written while the MEM_BUSY bit is set. MEM_ADDR: The indirect memory address indicates the word address within the memory table selected with the MEM_SELECT in the command register.
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Register 0x304: RDAT Indirect Memory Data LSB Bit 15:0 Type R/W Function MEM_DATA_LSB Default 0
This register should not be written while the MEM_BUSY bit is set. MEM_DATA_LSB: The MEM_DAT_LSB represents either: (1) the least significant 16 bits of the data to be written to internal memory or (2) the least significant 16 bits of the read data resulting from the previous read operation. The read data is not valid until after the MEM_BUSY bit has been cleared by the RDAT. The actual definition of each memory table is described under the Indirect Memory Data MSB Register description.
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Register 0x306: RDAT Indirect Memory Data MSB Bit 15:0 Type R/W Function MEM_DATA_MSB Default 0
This register should not be written while the MEM_BUSY bit is set. MEM_DATA_MSB: The MEM_DAT_MSB represents either: (1) the most significant 16 bits of the data to be written to internal memory or (2) the most significant 16 bits of the read data resulting from the previous read operation. The read data is not valid until after the MEM_BUSY bit has been cleared by the RDAT. The actual definition of each memory table is described below. RDAT Link Statistics Memory The link statistics memory is maintained by RDAT; it stores pertinent cell and event counts for each link. Each cell may cause the oif_anomalies count to be incremented, and also may cause one and only one of the other counters to be incremented. All counters roll over unless otherwise noted. Each record is 4 words deep by 32 bits wide (each word contains two counts for IMA links, one count for TC Links); they are addressed by the physical link number. MEM_ADDR = (Physical Link Number X 4) + Word Offset Table 21 Word 0 Bits 31:16 15:0 RDAT Link Statistics Record (IMA) Parameter stuff_events oif_anomalies Description Count of the number of stuff events received on this link. Count of the number of times this link has transitioned from the IMA Sync state to the IMA Hunt state in the IFSM. Count of HEC errored, OCD errored, invalid, or missing ICP cells received on this link. This also includes valid ICP cells received at unexpected positions.
1
31:16
icp_violations
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Word
Bits 15:0
Parameter icp_cells filler_cells
Description Count of the number of valid, non-errored ICP cells received on this link. Count of the number of non-errored filler cells received on this link that have been written to the buffer. Count of the number of user cells received on this link that have been written to the buffer. Count of the cells which were not written to the delay compensation buffer while in the IMA enable state (primarily due to errored conditions such as HEC errors, filler cells with CRC-10 errors, invalid or errored ICP cells not at expected positions, overrun, OCD, LCD, OIF, LIF, , reader not active yet). Count of the number of cells dropped while the link is in IMA mode and not Enabled.
2
31:16
15:0
user_cells
3
31:16
filtered_cells
15:0
dropped_cells
Table 22 Word 0 1 2
RDAT Link Statistics Record (TC) Parameter Description Reserved. Reserved. user_cells Count of the number of user cells received on this link that have been written to the buffer. Reserved
3 RDAT IMA Group Statistics Memory
The RDAT IMA Group Statistics Memory is maintained by the RDAT; it stores pertinent cell and event counts for up to 4 groups. All counters roll over unless
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otherwise noted. Each record is 4 words deep by 32 bits wide, and is addressed by the group tag. MEM_ADDR = (Group Tag X 4) + Word Offset Table 23 Word 0 RDAT IMA Group Statistics Record Parameter atm_cells Description Count of the number of cells that have been read from the DCB and transferred to the ATM layer for this group. Count of the number of cells which have been dropped solely due to ATM layer congestion for this group. Count of the number of filler cells that have been read from the DCB (and not transferred to the ATM layer) for this group. Buffers that either: (1) do not contain the correct link_sequence number or pointer or (2) do not have the valid bit set - these buffers will match this criteria. The cell writer may mark cells in this manner for many reasons; for example, when the link is not yet IMA enabled.
1
dropped_cells
2 3
reserved filler_cells
RDAT TC Group Statistics Memory The RDAT TC group statistics memory is maintained by the cell reader block; it stores pertinent cell and event counts for up to 8 TC links. All counters roll over unless otherwise noted. Each record is 2 words deep by 32 bits wide, and is addressed by the TC tag. MEM_ADDR = (TC Tag X 2) + Word Offset
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Table 24 Word 0
RDAT TC Group Statistics Record Parameter atm_cells Description Count of the number of cells which have been read from the DCB and transferred to the ATM layer for this TC group. Count of the number of cells which have been dropped solely due to ATM layer congestion for this group.
1
dropped_cells
RDAT Validation Memory The RDAT Validation record contains configuration information for a physical link. This memory is configured by the RIPP (via the IMPB interface) for IMA operation; it is used by the cell writer to validate incoming ICP cells and to control the flow of data to the delay compensation buffers. For a link which is to be used for TC only mode, the single bit tc_mode bit must be programmed. All other bits are maintained by the S/UNI-IMA-8 and should be set to zero at link configuration. Each record is two words by 32 bits wide, and is addressed by the physical link number. MEM_ADDR = Physical Link Number Table 25 Word Bits 0 31 RDAT Validation Record Parameter tc_mode Description tc_mode controls whether the link is in TC mode or part of an IMA group 0 1 IMA link. Flow of cells is controlled by the IMA protocol and the current IMA state TC Enabled. Cells received for this link are stored in a shallow FIFO in the SDRAM and scheduled for immediate transmission out the group FIFO.
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Word Bits 0
Parameter
Description Link Data State. Valid only in IMA mode. This state is reports the current state as set may by the RIPP to determine how the RDAT should handle incoming cells: 00 01 Disabled. Cells are read from the link FIFOs and dropped. IMA startup. All ICP cells are forwarded to the RIPP via the ICP FIFO, but the IFSM is not started and the delay compensation buffers remain idle for this link. IMA Monitor. The IFSM is enabled. ICP cells are forwarded to the RIPP (all during the IFSM HUNT state, just cells at the expected ICP cell position during the PRESYNC and SYNC states). No cells are written to valid buffer locations in the DCB, but the write pointers are incremented. IMA Enabled. Same as IMA Monitor, except that user and filler cells are written to the DCB.
30:29 link_state
10
11
28:26 25:24 m
Reserved. IMA frame length. The value is programmed by the RIPP to allow the RDAT to perform the IFSM, and to validate the value for M in the incoming ICP cells. 00 01 10 11 32 cells 64 cells 128 cells 256 cells.
23:16 ima_id
IMA ID. This value is the group identifier, which is programmed by the RIPP to allow the RDAT to validate this value in the incoming ICP cells.
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Word Bits 15:8
Parameter icp_offset
Description ICP Cell Offset. This value is programmed by the RIPP to allow the RDAT to determine the frame boundary on this link, and to validate this value in the incoming ICP cells. Reserved. IMA Version supported for this link. This will factor into IMA OAM label checking, if the label_disable bit is not set. 0 = IMA version 1.1 1 = IMA version 1.0
7 6 ima_version
5
label_disable
When set, the IMA OAM label within the incoming ICP cells will not be used for validation of these cells. When not set, the IMA OAM label must match that specified by the ima_version field. Logical identifier for this link. This value is programmed by the RIPP to allow the RDAT to validate the incoming ICP cells. Reserved. Configured overrun threshold of the delay compensation buffer for this link (in cells - IMA only). This must be less than or equal to the value specified in MAX_DCB_DEPTH in the Global configuration register. When this threshold is exceeded (distance between the read and write pointers), the overrun_latch error status will be set. This threshold is programmed by the RIPP at link startup.
4:0
lid
1
31:10 9:0 dcb_thresh
RDAT Link Context Memory The RDAT Link Context memory contains state information for a physical link. For TC only connections, this memory should be initialized to zero. For IMA connections, this memory is used by the RDAT to maintain the IFSM, IESM, OSM, and the DCB write pointer for a link. Each record is two words by 32 bits wide, and is addressed by the physical link number.
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MEM_ADDR = (Physical Link Number x 2) + Word Offset Table 26 Word Bits 0 31 RDAT Link Context Record Parameter lcd_latch Description Loss of Cell Delineation Defect latched status. This status is maintained by the RDAT to report occurrences of LCD on this link. This bit will be set when an LCD defect is detected (as reported in the HEC field), and will be cleared by the RDAT when a valid ICP cell is received. The bit may remain set if the LCD condition persists. DCB Overrun latched status. This status is maintained by the RDAT to report occurrences of DCB overrun. This bit will be set when a DCB overrun is detected, and will be cleared by the RDAT when a valid ICP cell is received. The bit may remain set if the overrun condition persists. DCB Underrun latched status. This status is maintained by the RDAT to report occurrences of DCB underrun. This bit will be set when a DCB underrun is detected (by the cell reader process), and will be cleared by the RDAT when a valid ICP cell is received. The bit may remain set if the underrun condition re-occurs. Reserved Reserved
30
overrun_latch
29
underrun_latch
28: 25 24:15
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Word Bits
Parameter
Description IMA Error/Maintenance State. This state is maintained by the RDAT to indicate the current state in the IESM for this link. 11 10 01 00 Reserved. IMA Working. User cells may be written to the DCB. OIF Anomaly. User cells are replaced with filler cells in the DCB. LIF Defect. User cells are replaced with filler cells in the DCB.
14:13 iesm_state
12:10 oif_cnt
Count of the number of IMA frames while in the Out of IMA Frame (OIF) anomaly. This value is compared against gamma + 2 to detect the loss of an IMA frame (LIF) Gamma is set in Register 0x308. Once the LIF condition has been detected, this count is reset, and is used to count the persistence of IMA Sync for 2 IMA frames. Active high bit indicating when the last cell received on this link was a stuff cell (required for proper IFSM processing). Reserved. The group tag associated with this link. The value is set by the read process; it is used by the cell write process to retrieve the group read pointer, in order to detect overrun conditions.
9
last_cell_stuff
8:2 1:0 group_tag
1
31 30
Reserved Reserved
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Word Bits 29
Parameter idleerr
Description Idle Cell Received during IMA status. This status is maintained by the RDAT to report occurrences of idle cells on IMA links to PM via the RIPP. This bit will be set when an idle cell is detected on an IMA link, and will be cleared when the RDAT message clear command is issued with the idleerr_clear bit set (indicating that the RIPP has acknowledged the problem). Reserved Current link stuff count. This indicates the occurrence of the next stuff event. When an ICP cell is received, this count is set to the value in the link stuff indication in that cell. In the event of an errored, invalid, or missing ICP cell, the count will be automatically decremented (unless the count is 000 or 111). Note that an invalid stuff sequence will be interpreted as an invalid ICP cell. 111 100 011 010 001 No imminent stuff event. Reserved. Stuff event in 4 ICP cell locations. Stuff event in 3 ICP cell locations. Stuff event in 2 ICP cell locations. Stuff event in 1 ICP cell locations. 110-101
28: 26 25:23 stuff_cnt
000 The next cell received on this link is a stuff event.
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Word Bits
Parameter
Description IMA Frame Synchronization Mechanism State. This state is maintained by the RDAT to indicate the current state in the IFSM for this link. 00 IMA Hunt. Performs a cell-by-cell search for IMA framing. Cells are not written to the DCB. 01 IMA PreSync. Performs a frame-by-frame search for valid ICP cells. Cells are not written to the DCB (although write pointers are maintained). 10 IMA Sync. Verifies IMA framing on a frame-by-frame basis. Valid cells are written to the DCB. 11 Reserved.
22:21 ifsm_state
20:18 state_cnt
State count. This count is used within the IFSM, and has dual meaning, depending on the state. In the IMA PreSync state, this is the current number of consecutive valid ICP cells. This value is compared against the device gamma value to determine when the IFSM may enter the IMA Sync state from the IMA PreSync state. Once the IMA Sync or Hunt state is entered, this value is reset to 0. In the IMA Sync state, this is the current number of consecutive errored ICP cells. This value is compared against the device beta value to determine when the IFSM may enter the IMA Hunt state from the IMA Sync state. Once the IMA Hunt state is entered, or a non-errored cell is received, this value is reset to 0.
17:16 invalid_cnt
Current number of consecutive invalid ICP cells. This value is compared against the device alpha value to determine when the IFSM may enter the IMA Hunt state from the IMA Sync state. Once the IMA Hunt state is entered, or a valid cell is received, this value is reset to 0, and this value may only be incremented in the IMA Sync state.
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Word Bits 15:0
Parameter write_ptr
Description Current delay compensation buffer write pointer for this link. The least significant portion of the write pointer is the cell number within the IMA frame, while the most significant portion represents the IMA Frame Sequence Number. The actual number of bits per field depends on the value for M for this link. Bits 9:0 for MAX_DCB_DEPTH = 1024 always represent the actual buffer write pointer (or bits 7:0 for MAX_DCB_DEPTH = 256). The write pointer is initialized by the RDAT when a valid ICP cell is received while in the IMA Hunt state, and is incremented otherwise. The most significant bits (not determined by the frame sequence number) will be synchronized to the group read pointer upper bits. (If the lower portion of the write pointer is less than the lower portion of the read pointer, then the write pointer upper bits will be set to one greater than the read pointer upper bits). Each increment of the write pointer represents a single cell time at the link line rate. All write pointers within a group can be compared in order to determine the differential delay.
RDAT Link Sequence Memory The RDAT Link Sequence memory contains the current link sequence number for each link. This information used solely by the RDAT for buffer management. Each record is one word by 10 bits wide, and is addressed by the physical link number. MEM_ADDR = Physical Link Number
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Table RDAT Link Sequence Memory Bits 9 Parameter msg_status Description RDAT message FIFO status. This bit is set by the RDAT when a message for this link is written to the RDAT message FIFO. The bit is cleared when a command for this link is written to the RDAT message clear command register. Reserved Reserved
8 7:0 Receive ICP Cell Buffer
The ICP cell buffer contains the most recently received non-errored ICP cell for each link. This buffer is provided for the RIPP, but is also read accessible from the microprocessor. Each buffer is 32 bits wide by 16 words, and is addressed by the physical link number. MEM_ADDR = (Physical Link Number X 16) + Word Offset Table 27 Word Bits Receive ICP Cell Buffer Structure Parameter icp_data Description Octets 6-53 of the payload contained in the last non-errored ICP cell for this link. 31:24 0 1 2 3 4 5 6 7 Octet 6 Octet 10 Octet 14 Octet 18 Octet 22 Octet 26 Octet 30 Octet 34 23:16 Octet 7 Octet 11 Octet 15 Octet 19 Octet 23 Octet 27 Octet 31 Octet 35 15:8 Octet 8 Octet 12 Octet 16 Octet 20 Octet 24 Octet 28 Octet 32 Octet 36 7:0 Octet 9 Octet 13 Octet 17 Octet 21 Octet 25 Octet 29 Octet 33 Octet 37
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Word Bits 8 9 10 11 12 31:10 9
Parameter
Description Octet 38 Octet 42 Octet 46 Octet 50 Reserved. Octet 39 Octet 43 Octet 47 Octet 51 Octet 40 Octet 44 Octet 48 Octet 52 Octet 41 Octet 45 Octet 49 Octet 53
position_error The current ICP cell was received in an unexpected position within the IMA frame. If the contents of the cell are valid, then the ICP cell is considered valid, but the IFSM will transition to the IMA Hunt state. header_invalid The ATM cell header is not a correct ICP cell header. cid_invalid label_invalid lid_mm ima_id_mm m_mm seq_error The Cell ID does not indicate the OAM Cell Type is ICP. The OAM Label does not indication IMA version 1.1. The link identifier in the current ICP cell does not match the LID in validation memory. The IMA ID in the current ICP cell does not match the IMA ID in validation memory. The IMA Frame Length in the current ICP cell does not match the length in validation memory. The IMA Frame Sequence Number in the current ICP cell does not match the sequence number maintained by the RDAT.
8 7 6 5 4 3 2
1 0 13:15
icp_offset_mm The ICP Cell Offset in the current ICP cell does not match the offset in validation memory. stuff_invalid The link stuff indication in the current ICP cell has not progressed properly from the previous value. Reserved.
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RDAT IMA Group Context Memory The RDAT IMA Group Context Memory contains state information maintained by the cell reader. This memory contains state information for up to 4 IMA groups. The only field in this structure that must be programmed is the vphy_id. Each record is 32 bits wide by 4 words, and is addressed by the group tag. MEM_ADDR = (Group Tag X 4) + Word Offset Table 28 Word Bits 0 RDAT IMA Group Context Record Parameter Description Virtual PHY ID. This identifies the address that will be prepended to all cells as they are written to the RXAPS FIFO. For multiple channel mode, the least significant 5 bits determine the destination channel of the RXAPS FIFO for this IMA group. For single channel mode, the least significant 7 bits must uniquely identify a channel (legal values of 0-7). Reserved. Reserved read_ptr Current read pointer for the delay compensation buffers associated with this group. The most significant bits represent an extension of the pointer, which is based on the IMA frame sequence number. This field is initialized at link addition using the DCB depth command (with the initiate bit set). Reserved Reserved.
31:16 vphy_id
15:0 1 31:16 15:0
2 3
31:0 31:0
RDAT TC Context Memory The RDAT TC Context Memory contains state information maintained by the cell reader. This memory contains state information for up to 8 TC connections. Each record is 32 bits wide by 1 word, and is address by the TC tag.
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MEM_ADDR = TC Tag Table 29 Bits 31:16 RDAT TC Context Record Parameter vphy_id Description Virtual PHY ID. For UTOPIA mode, this identifies which channel in the RXAPS FIFO cells received for this group will be written to. For Any-PHY mode, this identifies the least significant bits of the address which will be prepended to all cells as they are written to the single channel RXAPS FIFO. Current read pointer for the delay compensation buffers associated with this TC connection.
15:0
read_ptr
Receive ATM Congestion Count Register The receive ATM congestion count is incremented by the RDAT each time a cell is dropped due to ATM congestion. This is a global count. MEM_ADDR is not used for accesses to this register. Table 30 Bits 31:0 Receive ATM Congestion Count Register Parameter cong_count Description Count of the total number of cells dropped due to ATM congestion.
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Register 0x308: RDAT Configuration Bit 15 14:8 7:5 4:2 1:0 ALPHA: ALPHA represents the number of consecutive invalid ICP cells which will cause the IFSM to transition from the IMA Sync state to the IMA Hunt state. Value 0 1-2 3 BETA: BETA represents the number of consecutive errored ICP cells which will cause the IFSM to transition from the IMA Sync state to the IMA Hunt state. Value 0 1-5 6-7 GAMMA: GAMMA represents the number of consecutive valid ICP cells which will allow the IFSM to transition from the IMA PreSync state to the IMA Sync state. GAMMA+2 also represents the number of frames the IESM will wait after detecting OIF before entering the LIF state. Definition Undefined Number of consecutive errored ICP cells Undefined Definition Undefined Number of consecutive invalid ICP cells Undefined R/W R/W R/W Type R/W Function RDAT_ENABLE Unused GAMMA BETA ALPHA Default 0 0 1 2 2
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Value 0 1-5 6-7 RDAT_ENABLE:
Definition Undefined Number of consecutive valid ICP cells Undefined
When set, this bit enables the RDAT state machines. When disabled, the link FIFOs are not serviced and IDCC requests are ignored. The operation of the microprocessor accesses and the IMPB are not affected by this enable.
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Register 0x30A: Receive ATM Congestion Status Bit 15:8 7:0 Type R2C R2C Function Reserved CONG(7:0) Default 0 0
The status in this register is latched, and it is cleared when read. CONG(7:0): In multiple channel UTOPIA mode, a set bit indicates that a cell has been dropped due to a full ATM FIFO channel. In single channel mode, bits 7:1 are unused. Bit 0 indicates that a cell has been dropped because the single shared FIFO is full, or because 16 cells are already stored in the FIFO for the current group.
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Register 0x30E: Receive TC Overrun Status Bit 15:7 6:3 2:0 R Type Function Unused Reserved PHYSICAL_LINK Default 0 0 0
The status in this register is latched; it is cleared when read. PHYSICAL_LINK: Indicates the most recent physical link number that experienced the overrun condition.
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Register 0x310: RDAT Master Interrupt Status Bit 15 14:3 2 1 0 R2C RO RO Type RO Function Reserved Unused TC_OVERRUN Reserved ATM_CONG Default 0 0 0 0 0
ATM_CONG_LSB: When set, this bit indicates that an interrupt is present in the ATM Congestion Status LSB register. This bit will be cleared when no interrupt conditions are present in that register, or when the conditions are not enabled using the ATM Congestion Interrupt Enable LSB register. ATM_CONG_MSB: When set, this bit indicates that an interrupt is present in the ATM Congestion Status MSB register. This bit will be cleared when no interrupt conditions are present in that register, or when the conditions are not enabled using the ATM Congestion Interrupt Enable MSB register. TC_OVERRUN: When set, this bit indicates that an external FIFO (SDRAM) overrun has occurred on the physical link indicated in the TC Overrun status register. Note that this condition will only occur if the setup procedures are not followed properly by PM. This bit will be cleared when this register is read.
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Register 0x312: Receive ATM Congestion Interrupt Enable Bit 15:8 7:0 Type R/W R/W Function Reserved CONG_INTR_EN(7:0) Default 0x0000 0x0000
CONG_INTR_EN(7:0): The CONG_INTR_EN vector enables the ATM FIFO congestion status for RDAT_INTR interrupt generation. When a bit is a one, the associated status will generate an interrupt.
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Register 0x316: RDAT Master Interrupt Enable Bit 15 14:3 2 1 0 R/W R/W R/W Type R/W Function Reserved Unused OVERRUN_INTR_EN Reserved CONG_INTR_EN Default 0 0 0 0 0
CONG_INTR_EN: When set to a one, the CONG_INTR_EN allows the presence of an enabled interrupt in the ATM Congestion Status register to cause an RDAT interrupt. OVERRUN_INTR_EN: The OVERRUN_INTR_EN bit enables the TC overrun status for RDAT_INTR interrupt generation. When the enable bit is a one, a TC overrun will generate an interrupt.
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11.9 TIMA registers Register 0x320: TIMA Indirect Memory Command Bit 15 14 13:3 2:0 R/W Type R R/W Function MEM_BUSY MEM_RWB Unused MEM_SELECT Default 0 0 0 0
Writing to this register triggers an indirect memory access to the TIMA Context tables. The indirect memory address (and data register for write operations) must be configured prior to writing this register. MEM_SELECT: The indirect memory select indicates the memory table (or register bank) within the TIMA which will be accessed. MEM_SELECT 0 0 1 2 3-7 MEM_RWB: The memory indirect access control bit (MEM_RWB) selects between a configure (write) or interrogate (read) access to the TIMA internal. Writing a logic 0 to MEM_RWB triggers an indirect write operation. Data to be written is taken from the Indirect Memory Data registers. Writing a logic 1 to MEM_RWB triggers an indirect read operation. The read data can be found in TIMA Memory Table Transmit IMA Group Context Table Memory Transmit IMA Group Configuration Record Transmit LID to Physical Link Map Memory Transmit Link Context Table Memory Reserved Address Range 0-31 (0-0x01F) 672 - 675 (0x2A0 - 0x2A3) 0-127 (0x0-0x07F) 0- 15 (0x0- 0xF)
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the Indirect Memory Data registers. The address within a memory table can be found in the Indirect Memory Address register. MEM_BUSY: The indirect memory access status bit (MEM_BUSY) reports the progress of an indirect access. A write to the Indirect Memory Command register triggers an indirect access and sets MEM_BUSY to a logic 1; MEM_BUSY will remain logic 1 until the access is complete. This register should be polled to determine when data from an indirect read operation is available in the TIMA Indirect Memory Data registers or to determine when a new indirect write operation may commence. Register 0x322: TIMA Indirect Memory Address Bit 15:11 10:0 R/W Type Function Unused MEM_ADDR Default 0 0
This register provides the address for indirect memory access to the TIMA Context tables. MEM_ADDR: The indirect memory address indicates the word address within the memory table selected with the MEM_SELECT in the TIMA Indirect Memory Command register.
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Register 0x324: TIMA Indirect Memory Data LSB Bit 15:0 Type R/W Function MEM_DATA_LSB Default 0
This register should not be written while the MEM_BUSY bit is set. MEM_DATA_LSB: The MEM_DATA_LSB represents either: (1) the least significant 16 bits of the data to be written to internal memory or (2) the least significant 16 bits of the read data resulting from the previous read operation. The read data is not valid until after the MEM_BUSY bit has been cleared by the TIMA. The actual definition of each memory table is described under TIMA Indirect Memory Data MSB. If a memory location is read which does not support any bits of 15:0, then the corresponding register bit is loaded with 0. If a memory location is written which does not support bits 15:0, then the data in the corresponding register bit is ignored.
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Register 0x326: TIMA Indirect Memory Data MSB Bit 15:0 Type R/W Function MEM_DATA_MSB Default 0
This register should not be written while the MEM_BUSY bit is set. MEM_DATA_MSB: The MEM_DATA_MSB represents either: (1) the most significant 16 bits (31:16) of the data to be written to internal memory or (2) the most significant bits of the data resulting from the previous read operation. The read data is not valid until after the MEM_BUSY bit has been cleared by the TIMA. If a memory location is read which does not support bits 31:16, then corresponding register bits are loaded with 0. If a memory location is written which does not support bits 31:16, then data in the corresponding register bits is ignored. The actual definition of each memory table is described below: Transmit IMA Group Context Table Memory The Transmit IMA Group Context Table Memory contains state information and statistics for each group maintained by the transmit engine. Additionally, ICP cell information delivered by the RIPP is stored for each group. Data is organized into 4 records one for each of the maximum 4 IMA groups. Each record is 32 bits wide per word and 16 words deep. Each record is addressed by the group tag. MEM_ADDR = (Group Tag X 16) + Word Offset Table 31 Word 0 1 Transmit IMA Group Context Record Bits 31: 0 31:16 Discarded Cells Parameter Description Reserved. Number of cells discarded from ATM layer when the IMA group was in an nonoperational state. Reserved
15:0
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Word 2
Bits 31:0
Parameter Number of Cell Per Group
Description Continuously running cell count of all ATM cells read from the associated group FIFO and sent to link FIFOs. Maintained by TIMA state machine. Continuously running cell count of ATM filler cells (generated when there is no ATM cell to send) delivered on all links in the group. Maintained by TIMA state machine. Reserved Configuration bit maintained by RIPP to denote the current GTSM state for the associated group. When set to 1 the group is considered active. When set to 0 the group is inactive and all enabled links will have filler cells sent on them regardless of whether they are active or inactive. ICP cell octets that are maintained by RIPP and placed into the outgoing ICP cells for all links in the group.
3
31:0
Number of ATM Filler Cells
4 5
31:0 31:24 Unused
23:16 15:8 7:0 6 31:0
ICP octet 11 ICP octet 12 ICP octet 13 ICP octet 14 ICP octet 15 ICP octet 16 ICP octet 17 ICP octet 18 ICP octet 19 ICP octet 20 ICP octet 21 ICP octet 22 ICP octet 23 ICP octet 24 ICP octet 25
7
31:0
8
31:0
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Word 9
Bits 31:0
Parameter ICP octet 26 ICP octet 27 ICP octet 28 ICP octet 29 ICP octet 30 ICP octet 31 ICP octet 32 ICP octet 33 ICP octet 34 ICP octet 35 ICP octet 36 ICP octet 37 ICP octet 38 ICP octet 39 ICP octet 40 ICP octet 41 ICP octet 42 ICP octet 43 ICP octet 44 ICP octet 45 ICP octet 46 ICP octet 47 ICP octet 48 ICP octet 49 ICP octet 50 ICP octet 51
Description
10
31:0
11
31:0
12
31:0
13
31:0
14
31:0
15
31:24 23:16 15:0
Reserved
Transmit Group Configuration Table Memory The Transmit IMA Group Configuration Table Memory contains configuration data programmed by the PM layer for each group maintained by the transmit engine. Data is organized into 4 records, with one record for each of the maximum 4 IMA
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groups. Each record is a 32 bit wide single word. Each record is addressed by the group tag added as an offset of the base address MEM_ADDR = 0x2A0 + Group Tag Table 32 Transmit Group Configuration Table Record Bits 31:23 22:16 VPHY Address Parameter Description Unused VPHY address (group FIFO number) which is assigned to this group. Maintained by PM This field should only be modified by the PM during group configuration. Unused Disable Cell Discard Configuration bit which determines if the ATM cell discarding feature is enabled for this group. When set to 0, ATM cells will be read and discarded from the group FIFO (one for each request) if there are no active links in the group. When set to 1, cell discarding will not occur for the group. Configuration bit which determines whether stuff cell advertising is done either 4 ICP cells ahead or 1 ICP cell ahead of the stuff event. This bit is maintained by the PM and read by the TIMA transmit state machine. This bit should be changed only on group startup, otherwise the number of cells between TRL stuff events will be corrupted. 0 = 1 ICP cell ahead; 1 = 4 ICP cells ahead 8 Stuff Mode Configuration bit which determines whether ITC or CTC stuff mode is actually used for this group. Note it is possible to advertise ITC Transmit Clock Mode in an ICP cell but still use a common clock and CTC stuff mode. This bit is maintained by the PM and read by the TIMA transmit state machine. 0 = ITC stuff mode, 1 = CTC stuff mode 7:0 OAM Label Static field to be inserted into octet 6 of ICP cells and
15:9 10
9
Stuff Advertise Mode
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OAM cells. Maintained by PM. Transmit LID to Phsical Link Mapping Table Memory The Transmit LID to Physical Link Mapping Table Memory contains the physical link tag associated with each of the 32 possible link IDs within a particular group of the 4 possible groups. Data is organized into a single linear table 128 7-bit entries deep with each physical link ID stored as an 7 bit value. In general, this table is sparsely populated since each of the 8 physical link tags can only exist in one location throughout the entire table. Each entry is addressed by using the group tag concatenated with the link ID (LID) as an index. MEM_ADDR = (Group Tag X 32) + LID value Table 33 Bits 6:3 2:0 Transmit LID to Physical Link Mapping Table
Description Reserved Physical Link for corresponding Group Tag and Link ID. Only values 0 to 7 are valid for this field.
Transmit Physical Link Context Table Memory The Transmit Physical Link Context Table Memory contains state information and statistics for each of the 8 possible physical links maintained by the transmit engine. The memory locations associated with a particular link are used for different purposes depending on whether a link is part of an IMA group or is, instead, part of a TC mode connection. Data is organized into 8 records, one for each of the maximum 8 links. Each record is 32 bits wide per word and 2-words deep. Each record is addressed by either the TC tag delivered from the IDCC or the physical link tag extracted from the Transmit LID to Physical Link mapping table. MEM_ADDR = (Physical Link Tag or TC Tag X 2) + Word Offset Table 34 Word Bits 0 TIMA Physical Link Context Record Parameter Description Unused
31:24 unused
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Word Bits
Parameter
Description IMA mode: this field is indexed by the Physical Link tag and is used to determine the cell count within a frame at which an ICP is to be inserted for the link. The width of the field used by the TIMA is dependent on the value of M used for the particular group and is shown in the following: M=256 ICP offset determined by bits [7:0] M=128 ICP offset determined by bits [7:1] M=64 ICP offset determined by bits [7:2] M=32 ICP offset determined by bits [7:3] The mapping of the ICP offset is set such that the offset should not have to be changed if M is changed. This field is read by the transmit engine and is maintained by the PM. Values 0 to 255 are valid. TC mode: this field is indexed by the TC tag delivered by the IDCC and is used to determine the VPHY ATM source FIFO associated with the TC connection. This field is read by the TIMA and is maintained by the PM. Only values 0 to 7 are valid.
23:16 ICP offset or TC mode VPHY address
15:9 8:6 Startup Cell Count
Reserved Cell count used to track the first four cells after startup sent into each link FIFO. Used to assert a read inhibit signal per link (TL_FIFO_READ_INHIBIT) until four cells have been written into the link FIFO so that the nominal 4 to 5 cell depth can be achieved. This field must be initialized to 4 by the PM before the link is enabled to ensure proper startup. However, if the link is to be used for either a low speed or high speed TC mode connection, this field must be initialized to a value of 0 to prevent any read inhibit. Maintained and used by TIMA. Reserved.
5:0
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Word Bits 1
Parameter
Description
31:16 IMA Mode Stuff Event Count
IMA mode: this field is indexed by the Physical Link tag and is used to store a continuously or TC Mode User running count of the number of Stuff Events Cell Count (upper inserted on the link. It is maintained by the transmit engine and is read by the PM. This field word)) should only be reset when the link is not enabled. TC mode: this field is indexed by the TC tag delivered by the IDCC and is used to store the upper 16-bit word of a continuously running 32bit count of the total number of ATM user cells sent on the link. It is maintained by the transmit engine and is read by the PM. This field should only be reset when the link is not enabled.
15:0
IMA mode: this field is indexed by the Physical Link tag and is used to store a continuously or TC Mode User running count of the number ATM user cells Cell Count (lower transferred on the link. It is maintained by the transmit engine and is read by the PM. This field word)) should only be reset when the link is not enabled. TC mode: this field is indexed by the TC tag delivered by the IDCC and is used to store the lower 16-bit word of a continuously running 32-bit count of the total number of ATM user cells sent on the link. It is maintained by the transmit engine and is read by the PM. This field should only be reset when the link is not enabled.
IMA mode Total User Cell Count
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Register 0x328 TX Link FIFO Overflow Status Bit 15:8 7:0 Type R R2C Function reserved Link_FIFO_OVERFLOW_STAT [7:0] Default 0 0
The link FIFO overflow status register reports whether a particular corresponding link FIFO has experienced an overflow event which occurs when a write operation is attempted to a full FIFO. Each bit is automatically cleared after a read operation. If an overflow event occurs the same cycle a read operation occurs, the set of a status bit overrides the clear operation. Link FIFO Overflow Status[7:0] On read, each bit reports the status of the corresponding link FIFO (1= overflow, 0 = no overflow). Each set overflow status bit is cleared after a read.
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Register 0x336 Interrupt Enable
Bit 15:1 0
Type R R/W Reserved
Function
Default 0 0
Link FIFO Overflow Interrupt Enable
The interrupt enable bits control whether the corresponding interrupt source will cause an interrupt on the INT output or will be masked. Link FIFO Overflow Interrupt Enable 1) link FIFO overflow interrupts will be enabled. 0) link FIFO overflow interrupts are not enabled. 11.10 TX IDCC registers Register 0x340: TXIDCC Indirect Link Access Bit 15 14 13:9 8:7 6:3 2:0 Type R R/W N/A R/W R/W R/W Function CBUSY LRWB Unused LSEL[1:0] Reserved LADDR[2:0] 0 Default 0 0 N/A 0
Writing to this register triggers an indirect channel register access. LADDR [2:0]: The indirect link address number (LADDR [2:0]) indicates the link to be configured or interrogated in the indirect link access. LSEL: LSEL selects the RAM to interrogate or configure.
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00 - Unused 01 - Link Table 10 - Reserved 11 - Reserved LRWB: The link indirect access control bit (LRWB) selects between a configure (write) or interrogate (read) access to the RAM. Writing logic 0 to LRWB triggers an indirect write operation. Data to be written is taken from the Indirect Link Data registers. Writing logic 1 to LRWB triggers an indirect read operation. CBUSY: The indirect access command bit (CBUSY) reports the progress of an indirect access. CBUSY is set high to trigger an indirect access; it will stay high until the access is complete. Once the access is complete, the CBUSY signal is reset by the TSB. This register should be polled to determine either: (1) when data from an indirect read operation is available in the Indirect Data register or (2) when a new indirect write operation may commence.
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Register 0x342: TXIDCC Indirect Link Data Register 1 Bit 15:8 7 6:0 TC Mode: If this bit is set, the associated link is in pass-through mode Type N/A R/W R/W Function Unused TC Mode Reserved Default N/A 0 0
11.11 RX IDCC registers Register 0x350: RXIDCC Indirect Link Access Bit 15 14 13:9 8:7 6:3 2:0 Type R R/W N/A R/W R/W R/W Function CBUSY LRWB Unused LSEL[1:0] Reserved LADDR[2:0] Default 0 0 N/A 0 0 0
Writing to this register triggers an indirect channel register access. LADDR [2:0]: The indirect link address number (LADDR [2:0]) indicates the link to be configured or interrogated in the indirect link access. LSEL: LSEL selects the RAM to interrogate or configure. 00 - Unused
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01 - Link Table 10 - Reserved 11 - Reserved LRWB: The link indirect access control bit (LRWB) selects between a configure (write) or interrogate (read) access to the RAM. Writing logic 0 to LRWB triggers an indirect write operation. Data to be written is taken from the Indirect Link Data registers. Writing logic 1 to LRWB triggers an indirect read operation. CBUSY: The indirect access command bit (CBUSY) reports the progress of an indirect access. CBUSY is set high to trigger an indirect access, and will stay high until the access is complete. Once the access is complete, the CBUSY signal is reset by the TSB. This register should be polled to determine when data from an indirect read operation is available in the Indirect Data register or to determine when a new indirect write operation may commence.
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Register 0x352: RXIDCC Indirect Link Data Register 1 Bit 15:8 7 6:0 TC Mode: If this bit is set, the associated link is in pass through mode. Type N/A R/W R/W Function Unused TC Mode Reserved Default N/A 0 0
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Register 0x366: DLL Control Status Bit 15:1 0 Type R R Function Reserved RUN Default X 0
The DLL Control Status Register provides information of the DLL operation. RUN: The DLL lock status register bit (RUN) indicates the DLL has locked. After system reset, RUN is logic zero until the DLL has locked. For proper operation the DLL must be indicate RUN. The RUN register bit is cleared only by a system reset .
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12
OPERATION
12.1 Hardware Configuration The S/UNI-IMA-8 is powered up with the line interface disabled. The Any-PHY/UTOPIA interface can be set up in different modes. The AnyPHY/UTOPIA interface will remain tri-state until configured and the respective RA_ENABLE/TA_ENABLE bits are set. 12.2 Start-Up The S/UNI-IMA-8 uses an internal DLL on SYSCLK to maintain low skew on the ram interface. When the chip is taken out of hardware reset, the DLL will go into hunt mode and will adjust the internal SYSCLK until it aligns with the external SYSCLK. The microprocessor should poll the RUN bit in DLL CONTROL STATUS register until this bit is set. At this point the entire chip with the exception of the microprocessor interface and the DLL are in reset. Before any configuration can be done, including accessing the ram, the chip must be taken out of software reset by clearing the SW_RESET bit in the Global Reset Register. Once taken out of reset, the internal ram reset procedure is automatically initiated. The microprocessor should poll the BIST_DONE bit in the Global Reset register to determine when the internal RAM reset is complete. While the internal ram is initializing, access to all internal rams are prohibited, accesses attempted during this period of time are ignored. Once the chip is taken out of reset, the external SDRAM should be cleared to all zeros to ensure no false CRC errors are reported. Access to the SDRAM is through the SDRAM Diagnostic access port as discribed in 12.6.1. At this point, the Any-PHY/UTOPIA interface is disabled and all Any-PHY/UTOPIA outputs are tri-stated. Also, the line side interfaces are disabled and all internal registers are in their reset state.
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12.3 Configuring the S/UNI-IMA-8 12.3.1 Configuring Clock/Data Interface The Clock/Data interface has 2 major modes, Channelized for E1/T1 traffic and unchannelized for other traffic types. Each link should be configured for channelized/unchannelized mode using the RCAS/TCAS link configuration registers. If configuring channelized links, the T1/E1 mode should be configured at the same time. One configured, the links are still disabled. The links must be mapped and provisioned (enabled) 12.3.1.1 Channelized
When channelized links are chosen, the RCAS/TCAS Framing Bit threshold must be configured to detect the gap in the clock for the framing bit/byte. This value is dependent upon frame type T1/E1, serial clock speed and REFCLK frequency. The Link Disable feature may be used when configuring a link to squelch all data from a link while it is being provisioned. For the Tx direction, the data sent in idle timeslots may be selected with the TCAS Idle Time-slot Fill data. For T1, all timeslots are used to carry the ATM cell data so all timeslots should be mapped to the same virtual link. A one-to-one mapping between physical links and virtual links is recommended. For E1, timeslots 0 and 16 are used for signaling data and do not contain ATM cell data. Therefore, timeslots 1-15 and 17-31 must be mapped and provisioned (enabled) to carry ATM cell data. All of the timeslots in a link should be mapped to the same virtual link. A one-to-one mapping between physical links and virtual links is recommended. For Fractional links, multiple fractional ATM flows may exist on the same physical link. Each flow should be mapped to a unique virtual link. There is a limit of 8 virtual links for the S/UNI-IMA-8.
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12.3.1.2
Unchannelized
Unchannelized is used for data streams that are not either T1 or E1 framed. When using the unchannelized interface, the user is responsible for providing a clock which has all framing or overhead bits gapped out. The S/UNI-IMA-8 receives/sources one bit of data for each clock pulse. The unchannelized mode allows a wider range of clock frequencies. As the serial line frequency increases, the number of links supported decreases. 12.3.1.3 Rules for Choosing Clock frequencies
SYSCLK(min) = Max((50MHz * Line Throughput(Mbps)/130 Mbps), REFCLK)
ae 4o o ae c c14 + NumLines * / Num.Lines * Line.Clock .Freq e 3 REFCLK(min)= maxc , c 4 * Line.Clock .Period 6 c e ae ae 4 * Line.Clock .Period o o3 Num.Linesmax c c / - 14 * c 4 e e REFCLK .Period
Table 35 Serial Frequency 1.544 Mhz 2.048 Mhz 2.304 Mhz # Links REFCLK SYSCLK Frequency Frequency
8 8 8
19.44 Mhz 19.44 Mhz 19.44 Mhz
20 Mhz 20Mhz 20 Mhz
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12.3.2 Configuring TC layer Options TC layer options in the transmit direction include scrambling and HEC generations. Scrambling should be set as required by the physical layer. TC layer options in the receive direction include descrambling, and interrupt reporting and error handling options. To properly support IMA applications, the TC layer functions should not filter out errored cells but pass them to the IMALAYER and let the IMA-LAYER filter them out. The options LCDOCDPASS, HCSPASS and UNASSPASS should be set for IMA applications. If these options are set for TC links, only the unassigned cells will not be filtered by the IMALAYER. When running IMA, there should never be any idle cells. If idle cells exist on an IMA link, it depends upon where the idle cells were inserted whether IDLEPASS is desired to be set. If the idle cells were incorrectly inserted by the TC layer, correct operation could be preserved in the face of errors if IDLEPASS is not set. If the idle cells are inserted by the link layer, correct operation may be perserved by setting IDLEPASS. The configuration options are programmed one link at a time by following the steps below:
*
RTTC/TTTC Programming Steps: 1. For each write access, wait until the LBUSY bit in the RTTC/TTTC Indirect Status Register is clear. Note that the LBUSY bit might not be ready for up to 86 REFCLK cycle after an access. 2. Once the BUSY bit is clear, write to the RTTC/TTTC Link Data Register to specifiy the desired configuration options for that link. 3. Next, write into the RTTC/TTTC Indirect Status register specifying the SPE and LINK that is about to be configured and whether this is to be a write or a read access, by clearing or setting the LWRB bit in this register.
12.3.3 UTOPIA Interface Configuration There is very little setup required to configure the Any-PHY/UTOPIA Interface. For typical operation, the following registers need to be written to select the mode
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of operation and the predefined address or address range of the S/UNI-IMA-8 and the number of active ports of the S/UNI-IMA-8.
* * * * *
Transmit Any-PHY/UTOPIA Cell available Enable Receive UTOPIA Cell Available Enable Transmit Any-PHY Address Config Register Receive Any-PHY/UTOPIA Config register Transmit Any-PHY/UTOPIA Config Register
Once the registers are written with the proper configuration information, the enable bit should be set to enable normal operation. 12.4 IMA_LAYER Configuration 12.4.1 Indirect access to internal memory tables The IMA-Layer operations are configured by internal memory tables. The access to these tables is by indirect access. The following procedure applies for the indirect accesses in the RIPP, RDAT, TIMA, TXIDCC, and RXIDCC blocks. 12.4.1.1 Write accesses
The indirect write access procedure is as follows: 1) Wait until the "BUSY" bit in the Block Indirect Memory Access Control Register is clear. 2) Once the BUSY bit is clear, write to the Block Data Indirect Data Register(s) to specifiy the data to be written for that link. 3) Next, write into the Block Indirect Memory Address register specifying the address that is about to be configured and then write Block Indirect Memory Command register to specifiy the table to be accessed and whether the access is to be a write or a read access, by clearing or setting the LWRB bit in this register. Note that is some instances, the Block Indirect Memory Address register is combined with the Block Indirect Memory Access Control Register
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12.4.1.2
Read Accesses
The indirect read access procedure is as follows: 1) Wait until the "BUSY" bit in the Block Indirect Memory Access Control Register is clear. 2) Once the BUSY bit is clear, write into the Block Indirect Memory Address register specifying the address that is about to be configured and then write Block Indirect Memory Command register to specifiy the table to ba accessed and whether the access is to be a write or a read access, by clearing or setting the LWRB bit in this register. Note that is some instances, the Block Indirect Memory Address register is combined with the Block Indirect Memory Access Control Register 3) Poll the "Busy" bit in the Block Indirect Memory Access Control until it is cleared. 4)Read returned data from the Block Data Indirect Data Register(s).
12.4.2 Configuring Links for Transmission Convergence Operations After all of the interfaces have been configured, in order to configure a link for ATM over T1/E1, the mapping from physical link to Any-PHY/UTOPIA address must be set and the link must be set to TC mode within the IMA sublayer. Also, all link based statistics should be cleared. For TC only links, all RIPP tables are not used and should not be programmed. 12.4.2.1 Transmitter
To map the physical link to a ANY-PHY/UTOPIA address, the VPHY address field must be programmed in the TIMA Physical Link Context Record for the physical link. All other fields in this table should be cleared to zero. This table may be accessed by the TIMA Indirect Memory access registers. To put the physical link into TC mode set the TC_MODE bit in the TXIDCC. This bit may be accessed by the TXIDCC Indirect Memory Access registers.
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12.4.2.2
Receiver
To map the physical link to an Any-PHY/UTOPIA address, the VPHY address field must be programmed in the RDAT TC Context Record for the physical link. All other fields in this table should be cleared to zero. This table may be accessed by the RDAT Indirect Memory access registers. The RDAT Link Statistics Record, the RDAT TC Group Statistics Record, the RDAT Link Context Memory should also be cleared to zero to reset the statistic counts. The RDAT Validation memory should be set to TC_MODE To put the physical link into TC mode, set the TC_MODE bit in the RXIDCC. This bit may be accessed by the RXIDCC Indirect Memory Access registers. Ensure that the RDAT_EN bit in the RDAT CONFIGURATION register is set. 12.4.3 Configuring For IMA Operations All IMA timeouts are programmable. In general, the default values result in ~1 sec timeouts with a 55 MHz SYSCLK. The global IMA interrupt enables default to disabled. In an interrupt driven system, these interrupt should be selectively enabled in registers 0x218, 0x21A, and 0x21C. RIPP_EN in Register -x200 controls whether internal IMA state machines engine is enabled. This must be set for proper operation. IMA groups are configured using the following per group tables:
* * * *
RIPP Group Configuration Record: Group options and configuration, TX LID to Link Mapping Table: maps Group Tag/LID to physical Link. TIMA TX Group Configuration Record: maps group to Any-PHY/UTOPIA port ID, sets stuffing mode and OAM label. RDAT IMA Group Context Record: maps group to Any-PHY/UTOPIA port ID
and also the following per link tables:
*
RIPP TX Link Configuration Record: maps physical Link to Group Tag/LID, enables TX Link Interrupts.
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* * *
12.4.3.1
RIPP RX Link Configuration Record: maps physical Link to Group Tag, enables RX link interrupts TIMA TX Physical Link Context Record: sets ICP offset. RDAT Link Context Record: maps physical link to group. Configuring a Group for IMA
IMA groups within the S/UNI-IMA-8 are identified by a "group tag". The group tag is an identifier with values from 0 to 3 that uniquely identifies the group for programming a reporting purposes within the S/UNI-IMA-8. The group tag is completely independent of the Group ID located within the ICP cells. Once a group tag is chosen for a group, the following records need to be programmed for the group: RIPP Group Configuration Record: Initial group options and configuration, After the group is started, the following configuration options may only be changed with a RIPP command or in conjunction with a group restart.
* * * * * *
Received OAM Label Group Symmetry IMA 1.1 versus IMA 1.0 IMA ID M Reported Clk Mode (ITC/CTC)
The following entries within the RIPP Group Configuration Record may be changed without a group restart of RIPP command. When changing these fields, care must be taken not the change other fields.
* * *
Minimum # of Links Differential delay tolerance and options per group Interrupt enables
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*
Rx Physical links that are in the group
TX LID to Link Mapping Table:
*
Select the LIDs to be used by the TX Links and program the physical links into the appropriate Group Tag/LID locations.
TIMA Group Configuration Record:
* * * *
TX VPHY ID Stuff Advertise Mode Actual stuffing mode(ITC/CTC) Transmitted OAM label.
RDAT IMA Group Context Record
*
RX VPHY ID
Also, while configuring a group, the context records that contain statistics should be initialized. The following records should be initialized to zero: RIPP group Context Record, RDAT IMA Group Statistics Record, Transmit IMA Group Context Record. 12.4.3.2 Configuring a Link for IMA
All link-based records are indexed by the physical link ID. Prior to configuring a link, the user should check to ensure that it is not in use already. This is necessary since link deletion from a group may take some time due to the necessity of allowing the DCB buffer for the link to drain. Reading the RX_ENABLE bit in the RIPP RX Link context record and the TX_ENABLE bit in the RIPP TX Link Context record can check this. The following fields in the following records need to be programmed; other fields in the records should be cleared to zero.
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RIPP TX Link Configuration Record
* * *
TX_LID Group Tag per link Interrupt enables
RIPP RX Link Configuration Record
* *
Group Tag per link Interrupt Enables
TIMA Physical Link Context Record
* *
ICP Offset Startup Cell Count = b'100
RDAT Link Context Record
*
Group Tag
Also, while configuring a link, the context records that contain statistics and assorted context should be initialized to zero. The following records should be initialized to zero: RIPP TX Link Context Record, RIPP RX Link Context Record, RDAT Link Statistics Record, RXIDCC Link Data TXIDCC Link Data 12.5 IMA Operations IMA operations are controlled via commands issued to the RIPP (Receive IMA protocol processor). In general, once started, the RIPP performs the hand
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shaking of state transitions between the near-end and far-end of an IMA connection. 12.5.1 Issuing a RIPP Command The RIPP commands control the LSM and GSM state machines. The group is identified by the group tag and the links involved are identified with a 32-bit vector. The TX_LINK_VEC has one bit for each TX LID and bit 0 indicates TX LID 0 and bit 31 indicates TX LID31. For symmetrical operations, the RX LIDs are not known until the ICP cells from a link are validated, the user controls the relationship between physical links and the RX Link vector through the RX Physical Link Table in the RIPP Group Configuration record. The RX physical Link Table should be configured according to the TX LID values. For example, the physical link ID for the Link with TX LID = 0 should be programmed as the RX physical link 0. When using the RIPP commands, the physical link entered for RX physical link 0 will be controlled by bit 0 of the RX_LINK_VEC and the physical link entered for RX Physical link 31 in the table will be controlled by bit 31 of the RX_LINK_VEC. For asymmetric operations, since there is not a TX link for each possible RX link and the RX LIDs are not known until the ICP cells from a link are validated, the user controls the relationship between physical links and the RX Link vector through the RX Physical Link Table in the RIPP Group Configuration record. There are no restrictions on how this table should be configured in asymmetrical mode. When using the RIPP commands, the physical link entered for RX physical link 0 will be controlled by bit 0 of the RX_LINK_VEC and the physical link entered for RX Physical link 31 in the table will be controlled by bit 31 of the RX_LINK_VEC. Note: There are 31 entries in the RPHY table even through a maximum of 8 links may be in the group to account for the LID. The RIPP command procedure is as follows: 1) Wait until the "CMD_BUSY" bit in the RIPP Command Register is clear. 2) Once the CMD_BUSY bit is clear, write the necessary data for the command registers 0x222 - -x22C (RIPP CMD_WR_DATA1 through RIPP CMD WR_DATA3).
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3) Write the RIPP CMD Register with the command code and group tag for the command. 4) Poll the "CMD_BUSY" bit in the RIPP Command Register and when cleared, check the status of the command. Commands may be rejected when illegal actions are requested. An example of an illegal action is to start a LASR when one is already in progress. 4) If the command was a "Read_event" or "Read Delay", the returned data can now be read from the RIPP Command Data Register Array located at addresses 0x240 - 0x2BE. 12.5.2 Summary of RIPP commands The following is a summary of all RIPP commands that are currently supported. For the detailed command bit encoding info, refer to the "registers" section. 1. Add_group Function Add 1 new group to the device. Note that this must be the first command to be issued to the group, if any other command is issued prior to this, it will be considered invalid and rejected. Group tag and vector of LIDS to be included in group Require configuration of all link and group records as detailed in 12.4.3.1 and 12.4.3.2. None.
Parameters Pre-requisite Restriction
2. Delete_group Function Parameters Pre-requisite Restriction Remove an existing group and all its links immediately. Group Tag None. None.
3. Restart_group
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Function Parameters Pre-requisite
Restart the specified group (GSM goes back to start-up state). Group Tag If any group configuration info need to be changed, PM must do so prior to issuing this command by writing to RIPP context memory (which in turn may require issuing Halt_group command first). None
Restriction
4. Inhibit_group Function Set the internal group inhibiting status flag. Once a group is considered inhibited, it will not go to OPERATIONAL state even if sufficient links exist in the group. If the group is already in OPERATIONAL state when the command is issued, the GSM will go to BLOCKED state and thus block the TX data path. However the RX data path remains on. Parameters Pre-requisite Restriction Group Tag None. None.
5. Not_inhibit_group Function Clear the internal group inhibiting status. If the group is currently in BLOCKED state and there are sufficient links in the group, the GSM will go to OPERATIONAL state. Group Tag None. None.
Parameters Pre-requisite Restriction 6. Start_LASR
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Function
Start LASR procedure on one or more links. The links involved may either be new links or existing links with a failure/fault/inhibiting condition. TX_LINK_VEC and RX_LINK_VEC are 32-bit vectors with the same bit mapping as TX_PHY_VALID or RX_PHY_VALID respectively, the bits corresponding to the new links are set to `1'. If the group configuration is symmetric, the TX_LINK_VEC and RX_LINK_VEC should be identical. Group Tag and vector of LIDS to be included in LASR Link records need to be properly initialized by PM prior to issue this command. Also RDAT/TIMA needs to be initialized properly to reflect the new links, if any. This command will be rejected if there is currently an active LASR procedure.
Parameters Pre-requisite
Restriction 7. Delete_link Function
Remove links from the group. The TX_LINK_VEC and RX_LINK_VEC fields indicate the links to be removed. If the group configuration is symmetric, the TX_LINK_VEC and RX_LINK_VEC should be identical. Group Tag and vector of LIDS to be deleted None. Deletion of a TRL Link is a special case. A group will not be able to operate normally without both the TX TRL and the RX TRL. Therefore, the TRL link should not be deleted unless it is the last link in the direction. Also, IMA protocol requires there to be at least 1 link in both directions, therefore PM should not delete the last link left in either direction in cases other than a complete group removal.
Parameters Pre-requisite Restriction
8. SET_RX_PHY_DEFECT Function Indicate to RIPP that the given link(s) have/have not physical
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defects (such as LOS/AIS) which is not detectable internally. TX_LINK_VEC and RX_LINK_VEC indicate the links affected. Parameters Pre-requisite Restriction Group Tag and vector of LIDS to be included in group None. None.
9. Unusable_link Function Indicate to RIPP that the given link(s) are unusable for certain reasons. TX_LINK_VEC and RX_LINK_VEC indicate the links affected. TX_CAUSE and RX_CAUSE indicates the reason for the link to be UNUSABLE. Note it is possible to change the cause for the link to be unusable even after it enters the unusable state. Parameters Pre-requisite Restriction Group Tag and vector of LIDS to be made unusable and the cause to report why the link is unusable None. It is required that PM must use one of the four defined causes (failed, fault, mis-connected, inhibited) if an unusable cause is to be reported to the far-end via the ICP cell.
10. Update_test_ptn Function Update the TX test pattern info to be sent in the outgoing ICP cells for the group. This command also causes the SCCI field in the next outgoing ICP cell to increase. Group Tag and TX Test pattern and Test pattern LID None. None.
Parameters Pre-requisite Restriction
11. Update_tx_trl Function Update the transmit timing information (TX TRL and clock
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mode) to be sent in the outgoing ICP cells. The TRL is also used to control the TX IDCC. This command also causes the SCCI field in the next outgoing ICP cell to increase. Parameters Pre-requisite Restriction Group Tag and LID for new TRL None. It is up to the user to pick a valid TRL to satisfy the requirement in the IMA spec. At least, a TRL that is currently configured to be in the group should be selected; otherwise the group will not be able to operate normally.
12. Read_event Function Read and clear the latched event status of the specified group and all its' links. The result read from the internal context memory is stored in Cmd_rd_data00 through cmd_rd_data1F. Refer to the "registers" section for further details. Parameters Pre-requisite Restriction 13. Read_delay Function Read all the DCB write pointers and link defect status of all links in the specified group. The result is stored in Cmd_rd_data00 through cmd_rd_data1F. Refer to the "registers" section for further details. Parameters Pre-requisite Restriction Group Tag None. None. Group Tag None. This command will be rejected on Deleted groups.
14. Adjust_delay
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Function
Start an adjust_delay procedure on the specified group. The amount of delay to be removed/added is specified as part of parameters. Group Tag and amount of delay in cells None. This command will be rejected if there is currently another adjust_delay procedure in progress or if there is currently a group-wide procedure (group start-up or LASR) in progress.
Parameters Pre-requisite Restriction
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12.5.3 Adding a Group In order to add a group, the Group and Link configuration should be performed. Next, the Add_Group command should be issued. This command will initiate the Group and Link State Machines. Is starts the GSM arbitration and automatically starts a LASR procedure. The Add_Group command continues after the CMD_ACK is returned. The completion of the command is generally indicated by an event that indicated either that the process timed-out or the group has become operational. If a timeout occurs, plane management should take appropriate action and either restart the group with new parameters or add additional links to the group. The event that indicates that the Add_Group command has completed successfully is either the GTSM_INT with the GTSM state = Operational or GSM_INT with the GSM state = Operational. Events that indicate that the Add_Group command has completed but was not successful are the following: NE_ABORT_INT FE_ABORT_INT GROUP_TIMEOUT_INT FE_TIMEOUT_INT Events that indicate that individual links are experiencing problems and did not become active are the following: DIFF_DELAY_INT INVALID_ICP_INT RX_TIMEOUT_INT TX_TIMEOUT_INT In order to track the progress of the command, interrupts may be enabled for GSM state changes and for the LSM state changes for all of the links. This may result in a large number of events if the group includes a large number of links. NOTE: If the TRL link is not validated on the RX side, since the group does not have a valid TRL, the group will not come up and will not report any events. If this happens, a Restart_group command must be executed to recover.
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12.5.4 Deleting a Group There are two methods of bringing a group down. To bring a group down and preserve data that has already been transmitted, it is recommended that the links be deleted first using the Delete_link command. This will result in the GSM transitioning to the insufficient links state when the number of active links falls below the minimum required links. Once the delete links is complete and all of the accumulated DCB data is played out, the Delete_group command deletes the existing group. To determine if the deleted links have all of the DCB data played out, the TX_LINK_EN and RX_LINK_EN bits may be polled in the RIPP Link Context records. Once the Delete_group command is executed, all links within the group will immediately stop transmitting IMA frames, and all received cells queued in the DCB buffer will be dropped. If data preservation is not a concern, a group may be removed immediately by issuing the Delete_group command. It is recommended that interrupts be disabled prior to the group deletion since the group deletion itself causes an interrupt to occur. If a Read_event command is issued on a deleted group, the command will be rejected. If interrupts are not disabled, care must be taken to ensure proper servicing of the RIPP Interrupt FIFO prior to reusing the group to avoid overrunning the RIPP Interrupt FIFO (interrupt from group prior to deletion and interrupt from group after re-use both in FIFO, and the FIFO is sized to have a maximum of one event per group.) If a group is delete prior to links being deleted, some clean up needs to occur. The msg bit in the RDAT Sequence memory must be cleared. When clearing this bit, it must be done using a read modify write procedure to avoid changing the other reserved fields in that record. Modifying the reserved field may lead to incorrect operation.
12.5.5 Restart Group To restart a group or issue a local reset to a group, the Restart_group command is used. Upon a Restart_group, the specified group's GSM will immediately transition to the Start-up state and try to renegotiate the IMA parameters. This command should be used after changing the M values, IMA ID, group symmetry, or OAM value on a group.
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12.5.6 Inhibit Group/Not inhibit Group To move a GSM into/out of the Blocked state, the Inhibit_group and Not_inhibit_group commands may be used. These commands set a mode such that the current GSM state is not important. Once set to the inhibit mode, the GSM will go to the Blocked state instead of the Operational state. The Not_inhibit_group command must be executed to remove this setting. 12.5.7 Adding a link or Links to an existing Group (Start LASR) In order to add links to an existing group, the START_LASR command is used. Prior to issuing this command, the link configuration should be performed as in 12.4.3.2. The Start_LASR command will initiate the Link Addition and Slow Recovery Procedure. The LASR procedure is paced by either (1) all of the indicated links' LSMs transitioning to the appropriate states or (2) the programmed link timeouts in the presence of defective or slow links. The LASR procedure continues after the CMD_ACK is returned. While a LASR procedure is in process, no other LASR procedure may be started on the same group. The completion of the command is generally indicated by an event that indicated either that the process timed-out or the links have become operational. If a timeout occurs, plane management should take appropriate action and either restart the LASR procedure in the case that the handshaking was just slow or replace defective links. The event that indicates that the Start_LASR command has completed successfully for symmetrical groups is the TX_ACTIVE_INT for all links involved. Due to the group wide synchronization, this event should occur for all links simultaneously. For asymmetrical groups, the RX_ACTIVE_INT indicates the completion of the LASR for receive links. Events that indicate that individual links are experiencing problems and did not become active are the following: DIFF_DELAY_INT INVALID_ICP_INT RX_TIMEOUT_INT TX_TIMEOUT_INT If a timeout event occurs, another LASR procedure must be execute to continue attempting to bring links to the active state.
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In order to track the progress of the command interrupts may be enable the LSM state changes for all of the links. This may result in a large number of events if the group includes a large number of links. 12.5.8 Reporting Link Defects in the ICP cell LIF, LODS, and LCD defects are automatically detected and reported in the ICP cell by the S/UNI-IMA-8. Other physical layer defects such as LOS, OOF, AIS are not detected by the S/UNI-IMA-8. To enable reporting of these defects, the Set_rx_defect command is provided to force the contents of the RDI field in the ICP cell. 12.5.9 Faulting/Inhibiting Links The S/UNI-IMA-8 reports defects to the upper layer S/W and allows the upper layer S/W declare fault conditions based upon defect information. In order to force a link into a Fault or Failure state, the Unusable_Link command is used. This link can operate on multiple links at a time. Once executed, the LSM of the affected links are transitioned to the Unusable state. If inhibiting the link without data loss is required, it is necessary to specify the cause as "inhibited". Normally when inhibiting a link, the link has been active for a while. If a link is inhibited immediately after becoming active, data loss can occur. If the S/UNI-IMA-8 has not yet received ICP cells from the link that indicates the link is active when the link is inhibited, data loss may occur. Note that links currently experiencing defect conditions will still experience loss of data even when inhibiting. When links are faulted, the existing data within the DCB is still played out on the ATM interface. 12.5.10 Change TRL
To change the TRL link, the Update_TRL command is used. The new TRL is immediately used for scheduling the group and will be reported as the TRL in the next ICP cell. If CTC timing is used, the stuffing is not affected. If ITC timing is used, the reference link is changed to the new TRL. The first stuff on the new TRL will occur on approximately the same frame as the stuff would have occurred when it was a non-reference link. After the first stuff on the new TRL, the new TRL will be stuffed every 2049 cells.
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12.5.11
Deleting a Link from a Group
A link can be deleted from a group by using the delete Link command. On the transmit side, the link will stop accepting ATM cells immediately and will transmit filler cells only. The links will be removed from the TX round-robin on the next frame boundary. On the receive side, the deleted link/links will transition to the Deleted state to ensure that all transmitted data is received into the DCB buffer. Once the FE TX state is detected as not active or the RX_LINK_DELETED timeout occurs, the RX links stop writing data to the DCB buffers. The DCB buffers allowed to underrun (preserving any previously stored data) prior to being disabled and removed from the receive round-robin. The RX_ENABLE bits and TX_ENABLE bits in the RIPP Link context records should be monitored to determine when the links can be reassigned to a different group. 12.5.12 Test Pattern Procedures
The test pattern procedure consists of 2 parts, issuing the test pattern and checking the test pattern. To issue a test pattern, the update_tst_ptn command is used. This starts the transmission of the new test pattern. The S/UNI-IMA-8 will always loopback the test pattern indicated in the ICP cell. Since each link may experience different round trip delays, the checking of the test pattern is split between the user and the S/UNI-IMA-8. The S/UNI-IMA-8 will compare test pattern received in the ICP cell with the test pattern that was sent on every received ICP cell. The S/UNI-IMA-8 stores the success or failure of this operation in the word 9 of the RIPP Group configuration register. The user is responsible for checking the results after a sufficient time has passed for a round trip delay on all links. NOTE: If no ICP cells are received for a particular LID, the RX_TEST_PTN_Match field is never updated. 12.5.13 IMA Events
All of IMA events are reported via a group-based structure. IMA events include link defects and link and group state machine changes. Any enabled IMA event will cause a RIPP_INTR. All IMA events may be enabled for reporting at the Goup/link level as well as a globally. Both the individual link/group enable as well as the global enable must be set to have an IMA event cause an RIPP_INTR.
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As enabled IMA events occur, a message is placed with the RIPP_INTR FIFO. Once a message is placed with the FIFO, another message will not be generated until the read_event command is executed for the group. During this period of time, additional events can accumulate and will be reported with the Read_event command when executed. The Read_event command queries the links within the group and provides all of the link and group information in a single data structure. To ease the processing load, a map that shows which links are experiencing INTR conditions is provided in page 0 of the returned status. Page 1 contains the interrupt conditions and page 2 provides the status. The majority of the error/interrupt processing may be performed with the information provided by the Read_event command. 12.5.14 End-to-end Channel Communication
According to the IMA spec, end-to-end channel is a proprietary communication channel via the corresponding field in the ICP cells. The S/UNI-IMA-8 provides access to this facility through the following means:
*
In the outgoing direction, the end-to-end channel may be updated by writing to the TX_END_CHANNEL field in the RIPP group configuration record at any time. In the incoming direction, the end-to-end channel information may be accessed by reading the ICP cell buffer memory area.
*
12.6 Diagnostic features 12.6.1 ICP Cell Trace The S/UNI-IMA-8 can be configured to forward incoming ICP cells to microprocessor, by setting the proper bits in the RIPP Group Configuration memory. The content of the forwarded ICP cell is stored in the ICP cell buffer registers. The ICP cell data exchange between RIPP and the microprocessor is controlled via the use of a lock bit (which is located in the ICP cell forwarding Control register) and the PM_ICP_AVL interrupt. The data exchange protocol is as follows: 1. S/UNI-IMA-8 sees a new ICP cell and starts polling the lock bit. 2. If the lock bit is current set, the cell is not forwarded.
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3. The ICP cell data content is copied to the ICP cell buffer registers. 4. The PM_ICP_AVL bit is set, this will cause an ICP_CELL_AVL_INT. 5. To read the ICP cell, the lock bit must be set by writing `1' to the ICP_FWD_LOCK_REQ bit in the ICP forwarding control register. Once the lock is granted when the ICP_FWD_LOCK_GRANT bit read back as `1'. The lock bit must be set prior to clearing the interrupt, otherwise it is possible to have multiple interrupt generated. 6. The interrupt should be cleared by reading the ICP cell forwarding status register. 7. The data may be readout from Forwarding ICP cell buffer registers. 8. The ICP_FWD_LOCK_REQ should be cleared bit by writing to the register location. 12.6.2 SDRAM Diagnostic access Diagnostic access of the external SDRAM is provided to enable SDRAM testing. The access to the SDRAM is provided on a cell buffer granularity. Each cell buffer is 64 bytes. By providing cell buffer burst access to the SDRAM, the SDRAM diagnostic accesses utilize the same burst access timing as is used when the S/UNI-IMA-8 is operating. Prior to performing any diagnostic accesses to the SDRAM, the SDRAM interface must be placed in diagnostic mode. In diagnostic mode, all automatic accesses from the S/UNI-IMA-8 (except refresh) are disabled and all accesses are controlled via the microprocessor interface. To write to the SDRAM, first the image of the cell must be written into the SDRAM DIAG Burst-Write RAM using the SDRAM DIAG Burst RAM Indirect Access. Once the image of the cell has been written, a command to transfer the data into the external SDRAM should be issued using the SDRAM DIAG WRITE CMD registers. The SDRAM DIAG WRITE CMD registers specify the address of the cell buffer to be written in the external SDRAM. For a read operation, a read command is issued using the SDRAM DIAG READ CMD registers. This command transfers data from the SDRAM into the internal cell buffer. When the command is complete as indicated by the RDBUSY bit in the command register, the data may be read out of the cell buffer using the SDRAM DIAG Burst RAM indirect access.
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Note that there is no CRC protection for data in diagnostic mode. By providing both Read Command registers and write command registers, a back-to-back read/write access may be performed to the SDRAM. 12.7 IMA Performance Parameters and Failure Alarms Support A number of IMA performance parameters and failure alarms are defined in the IMA spec (section 12.2.2) as a standardized interface to IMA unit management functions. The following text summarizes the support provided by S/UNI-IMA-8 to implement those functions. Table 36 Req. R-125 O-20 R-126 R-127 R-128 R-129 R-130 IMA Performance Parameter Support S/UNI-IMA-8 support
Performance parameter IV-IMA OIF-IMA SES-IMA SES-IMA-FE UAS-IMA UAS-IMA-FE TX-UUS-IMA
NE RX IMA defects will cause interrupts. RDI-IMA defects will cause interrupts. Derived from SES-IMA, no support. Derived from SES-IMA-FE, no support. S/UNI-IMA-8 provides read access to the TX LSM in RIPP link context records. Note after link start-up, it is up to PM to put the LSM into UNUSABLE state. S/UNI-IMA-8 provides read access to the RX LSM in link context records. Note after link start-up, it is up to PM to put the LSM into UNUSABLE state. S/UNI-IMA-8 may generate an interrupt once FE TX LSM enters UNUSABLE state. S/UNI-IMA-8 may generate an interrupt once FE RX LSM enters UNUSABLE state.
R-131
RX-UUS-IMA
R-132 R-133
TX-UUS-IMA-FE RX-UUS-IMA-FE
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R-134 R-135 O-21
TX-FC RX-FC TX-FC-FE
Failure condition is declared by PM, no support provided. Failure condition is declared by PM, no support provided. S/UNI-IMA-8 may generate an interrupt once FE TX LSM is in UNUSABLE state, PM may then read the FE LSM state in the RIPP context memory to determine the case. S/UNI-IMA-8 may generate an interrupt once FE RX LSM is in UNUSABLE state, or a RDI-IMA indication is sent by FE. S/UNI-IMA-8 provides counter of inserted stuff events per link. S/UNI-IMA-8 provide counter of received stuff events per link S/UNI-IMA-8 may generate an interrupt when a GTSM transition happens. S/UNI-IMA-8 provides interrupt and read access to internal context for various error conditions. See Table 37 for details. S/UNI-IMA-8 provides interrupt and read access to internal context for various error conditions. See Table 37 for details.
O-22
RX-FC-FE
O-23 O-24 R-136 R-137
TX-STUFF-IMA RX-STUFF-IMA GR-UAS-IMA GR-FC
O-25
GR-FC-FE
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Table 37 Req. R-138
IMA Failure Alarm Support Failure Alarm LIF S/UNI-IMA-8 support S/UNI-IMA-8 may generate an interrupt and latch the internal LIF error status once a link enters or exits LIF defect. S/UNI-IMA-8 may generate an interrupt and latch the internal LODS error status once a link enters or exits LODS defect. S/UNI-IMA-8 may generate an interrupt and latch the internal RDI-IMA status when RDI-IMA condition is entered or exited on a TX link. It is up PM to declare the alarm condition. It is up to PM to detect mis-connectivity on TX links, possibly through the use of test patterns. FE may indicate that the link is mis-connected by moving the RX LSM to corresponding UNUSABLE state, in which case RIPP will generate an interrupt and latch the error status.
R-139
LODS
R-140
RFI-IMA
R-141
TX-Mis-Connected
R-142
RX-Mis-Connected
It is up to PM to detect mis-connectivity on RX links. One possible way is to utilize the RX_IMA_ID field in the group context. Instead of letting RIPP capture the RX_IMA_ID from incoming ICP cells, PM can choose to initialize the group context with a expected RX_IMA_ID and set the RX_IMA_ID_VALID field to `1'. In this case the mis-connected RX links will likely to have a wrong IMA ID value and will not come up, which will eventually cause an interrupt. Also PM may utilize the test pattern procedure for this purpose.
O-28
TX-Fault
It is up to PM to declare fault conditions on TX links. To facilitate this, RIPP provides read access to the
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NE/FE LSM and GSM states in the context memory. O-29 RX-Fault It is up to PM to declare fault conditions on RX links. To facilitate this, RIPP provides read access to the NE/FE LSM and GSM states in the context memory. S/UNI-IMA-8 may generate an interrupt and latch the internal FE_TX_Unusable error status, once FE TX LSM enters UNUSABLE state. S/UNI-IMA-8 may generate an interrupt and latch the internal FE_RX_Unusable error status, once FE RX LSM enters UNUSABLE state. S/UNI-IMA-8 may generate an interrupt if a FE GSM state transition occurs. PM may then read the FE GSM state from the RIPP context memory. S/UNI-IMA-8 may generate an interrupt and latch the internal Config-Aborted error status, once it decides the FE parameters are unacceptable and the GSM should go to Config-Aborted state. S/UNI-IMA-8 may generate an interrupt and latch the internal Config-Aborted-FE error status, once it detects the FE GSM is in Config-Aborted state. S/UNI-IMA-8 may generate an interrupt if GSM state transition occurs. PM may then read the GSM state from the RIPP context memory. S/UNI-IMA-8 may generate an interrupt if a FE GSM state transition occurs. PM may then read the FE GSM state from the RIPP context memory. S/UNI-IMA-8 may generate an interrupt if a FE GSM state transition occurs. PM may then read the FE GSM state from the RIPP context memory. S/UNI-IMA-8 may generate an interrupt and latch the relevant error status, once it detects a mismatch between TX and RX clock modes.
R-143
TX-Unusable-FE
R-144
RX-Unusable-FE
R-145
Start-up-FE
R-146
Config-Aborted
R-147
Config-Aborted-FE
R-148
Insufficient-Links
R-149
Insufficient-Links-FE
R-150
Blocked-FE
R-151
GR-Timing-Mismatch
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13
FUNCTIONAL TIMING This section shows the functional relationship between inputs and outputs. No propagation delays are shown.
13.1 Receive Link Input Timing The timing relationship of the receive clock (RSCLK[n]) and data (RSDATA[n]) signals of an unchannelized link is shown in Figure 25. The receive data is viewed as a contiguous serial stream. There is no concept of time-slots in an unchannelized link. Each eight bits is grouped together into a byte with arbitrary alignment. The first bit received (B1 in Figure 25) is deemed the most significant bit of an octet. The last bit received (B8) is deemed the least significant bit. Bits that are to be processed by the S/UNI-IMA-8 are clocked in on the rising edge of RSCLK[n]. Bits that should be ignored (X in Figure 25) are squelched by holding RSCLK[n] quiescent. In Figure 25, the quiescent period is shown to be a low level on RSCLK[n]. A high level, effected by extending the high phase of the previous valid bit, is also acceptable. Selection of bits for processing is arbitrary and is not subject to any byte alignment or frame boundary considerations. Figure 25 - Unchannelized Receive Link Timing
RSCLK[n] RSDATA[n]
B1 B2 B3 B4 X B5 X X X B6 B7 B8 B1 X
The timing relationship of the receive clock (RSCLK[n]) and data (RSDATA[n]) signals of a channelized T1 link is shown in Figure 26. The receive data stream is a T1 frame with a single framing bit (F in Figure 26) followed by octet bound timeslots 1 to 24. RSCLK[n] is held quiescent during the framing bit. The RSDATA[n] data bit (B1 of TS1) clocked in by the first rising edge of RSCLK[n] after the framing bit is the most significant bit of time-slot 1. The RSDATA[n] bit (B8 of TS24) clocked in by the last rising edge of RSCLK[n] before the framing bit is the least significant bit of time-slot 24. In Figure 26, the quiescent period is shown to be a low level on RSCLK[n]. A high level, effected by extending the high phase of bit B8 of time-slot TS24, is equally acceptable. In channelized T1 mode, RSCLK[n] can only be gapped during the framing bit. It must be active continuously at 1.544 MHz during all time-slot bits. Time-slots can be ignored by
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setting the PROV bit in the corresponding word of the receive channel provision RAM in the RCAS block to low. Figure 26 - Channelized T1 Receive Link Timing RSCLK[n] RSDATA[n]
B7 B8 F B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 TS 24 TS 1 TS 2
The timing relationship of the receive clock (RSCLK[n]) and data (RSDATA[n]) signals of a channelized E1 link is shown in Figure 27. The receive data stream is an E1 frame with a single framing byte (F1 to F8 in Figure 27) followed by octet bound time-slots 1 to 31. RSCLK[n] is held quiescent during the framing byte. The RSDATA[n] data bit (B1 of TS1) clocked in by the first rising edge of RSCLK[n] after the framing byte is the most significant bit of time-slot 1. The RSDATA[n] bit (B8 of TS31) clocked in by the last rising edge of RSCLK[n] before the framing byte is the least significant bit of time-slot 31. In Figure 27, the quiescent period is shown to be a low level on RSCLK[n]. A high level, effected by extending the high phase of bit B8 of time-slot TS31, is equally acceptable. In channelized E1 mode, RSCLK[n] can only be gapped during the framing byte. It must be active continuously at 2.048 MHz during all time-slot bits. Time-slots can be ignored by setting the PROV bit in the corresponding word of the receive channel provision RAM in the RCAS block to low. Figure 27 RSCLK[n] RSDATA[n]
B6 B7 B8 F1 F2 F3 F4 F5 F6 F7 F8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 TS 31 FAS / NFAS TS 1 TS 2
- Channelized E1 Receive Link Timing
13.2 Transmit Link Output Timing The timing relationship of the transmit clock (TSCLK[n]) and data (TSDATA[n]) signals of a unchannelized link is shown in Figure 28. The transmit data is viewed as a contiguous serial stream. There is no concept of time-slots in an
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unchannelized link. Each eight bits is grouped together into a byte with arbitrary byte alignment. Octet data is transmitted from most significant bit (B1 in Figure 28) and ending with the least significant bit (B8 in Figure 28). Bits are updated on the falling edge of TSCLK[n]. A transmit link may be stalled by holding the corresponding TSCLK[n] quiescent. In Figure 28, bits B5 and B2 are shown to be stalled for one cycle while bit B6 is shown to be stalled for three cycles. In Figure 28, the quiescent period is shown to be a low level on TSCLK[n]. A high level, effected by extending the high phase of the previous valid bit, is also acceptable. Gapping of TSCLK[n] can occur arbitrarily without regard to either byte or frame boundaries. Figure 28 - Unchannelized Transmit Link Timing
TSCLK[n] TSDATA[n]
B1 B2 B3 B4 B5 B6 B7 B8 B1 B2
The timing relationship of the transmit clock (TSCLK[n]) and data (TSDATA[n]) signals of a channelized T1 link is shown in Figure 29. The transmit data stream is a T1 frame with a single framing bit (F in Figure 29) followed by octet bound time-slots 1 to 24. TSCLK[n] is held quiescent during the framing bit. The most significant bit of each time-slot is transmitted first (B1 in Figure 29). The least significant bit of each time-slot is transmitted last (B8 in Figure 29). The TSDATA[n] bit (B8 of TS24) before the framing bit is the least significant bit of time-slot 24. In Figure 29, the quiescent period is shown to be a low level on TSCLK[n]. A high level, effected by extending the high phase of bit B8 of time-slot TS24, is equally acceptable. In channelized T1 mode, TSCLK[n] can only be gapped during the framing bit. It must be active continuously at 1.544 MHz during all time-slot bits. Time-slots that are not provisioned to belong to any channel (the PROV bit in the corresponding word of the transmit channel provision RAM in the TCAS block set low) transmit the contents of the Idle Fill Time-slot Data register. Figure 29 - Channelized T1 Transmit Link Timing w/ Clock gapped Low TSCLK[n] TSDATA[n]
B7 B8 TS 24 B1 F B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 TS 1 TS 2
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Figure 30
- Channelized T1 Transmit Link Timing w/ Clock gapped high TSCLK[n]
TSDATA[n]
B7 B8 TS 24 F
B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 TS 1 TS 2
The timing relationship of the transmit clock (TSCLK[n]) and data (TSDATA[n]) signals of a channelized E1 link is shown in Figure 31. The transmit data stream is an E1 frame with a single framing byte (FAS/NFAS in Figure 31) followed by octet bound time-slots 1 to 31. TSCLK[n] is held quiescent during the framing byte. The most significant bit of each time-slot is transmitted first (B1 in Figure 31). The least significant bit of each time-slot is transmitted last (B8 in Figure 31). The TSDATA[n] bit (B8 of TS31) before the framing byte is the least significant bit of time-slot 31. In Figure 31, the quiescent period is shown to be a low level on TSCLK[n]. A high level, effected by extending the high phase of bit B8 of time-slot 31, is equally acceptable. In channelized E1 mode, TSCLK[n] can only be gapped during the framing byte. It must be active continuously at 2.048 MHz during all time-slot bits. Time-slots that are not provisioned to belong to any channel - i.e., the PROV bit in the corresponding word of the transmit channel provision RAM in the TCAS block is set low - transmit the contents of the Idle Time-slot Fill Data register. Figure 31 TSCLK[n] TSDATA[n]
B6 B7 B8 TS 31 B1 FAS / NFAS B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 TS 1 TS 2
- Channelized E1 Transmit Link Timing w/ Clock gapped Low
Figure 32 TSCLK[n] TSDATA[n]
- Channelized E1 Transmit Link Timing w/ Clock gapped How
B6 B7 B8 TS 31 FAS / NFAS
B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 TS 1 TS 2
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Alternatively, the CTSCLK can be used instead of the TSCLK[n] to lock the clocks of all the links together 13.3 Any-PHY/UTOPIA L2 Interfaces While the following diagrams present representative waveforms, they are not an attempt to unambiguously describe the interfaces. The Pin Description section is intended to present the detailed pin behavior and constraints on use. The following parameters apply to all Any-PHY/UTOPIA interface figures: m = 7 for 8-bit mode, 15 for 16 bit mode k = is a function of 8/16 bit mode and number of prepends selected. 13.3.1 UTOPIA L2 Transmit Slave Interface Figure 33 gives an example of the functional timing of the transmit interface when configured as a 31-port UTOPIA L2 compliant transmit slave. The interface responds to the enabled addresses as defined by the register Transmit Cell Available Enable by asserting the TCA corresponding to the addressed PHY when it is capable of accepting a complete cell. As a result, the master selects one of the S/UNI-IMA-8's PHYs by presenting the PHY address again during the last cycle TENB is high. If the device had not been selected, TSOC, TDAT[m:0], and TPRTY would have remained high-impedance. Figure 33 illustrates that a cell transfer may be paused by deasserting TENB. The device is reselected by presenting the PHY's address the last cycle TENB is high to resume the transfer.
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Figure 33
TCLK TADR[4:0]
- UTOPIA L2 Transmit Slave
DEV 1
IMA-PHY-X
DEV 3
IMA-PHY-X
DEV 2
1 TCLK TCA TDAT[m:0], TPRTY TENB TSOP
Data K-3 Data K-2 Data K-1 Data K Data 0 Data 1
13.3.2 Any-PHY Transmit Slave Interface Figure 34 gives an example of the functional timing of the transmit interface when configured as an 8-port Any-PHY compliant transmit slave. The Any-PHY master polls the ports in the S/UNI-IMA-8 and the S/UNI-IMA-8 device responds by driving TPA. If the S/UNI-IMA's polled port is capable of accepting a complete cell, TPA is driven active otherwise the TPA is driven inactive. Positive responses are recorded by the master and will eventually result in a data transfer. Ports are selected for data transfers via an in-band address prepend in first word of the data transfer. Polling continues independent of the data transfer state. Data transfers are initiated with the assertion of TENB and TSX; they complete without pausing.
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Figure 34
TCLK TADR[10:0] TCSB
- Any-PHY Transmit Slave
IMA-ADR
PHY 7
PHY 1
PHY 0
2 TCLK TPA TDAT[m:0], TPRTY TENB TSX TSOP
PHY 8 ADR Data 1 IMA-ADR Data 2 Data 3 Data K-1 Data K IMA-ADR PHY 1 Data 1
13.3.3 UTOPIA L2 Multi-PHY Receive Slave Interface Figure 35 gives an example of the functional timing of the receive interface when configured as a 31-port UTOPIA L2 compliant receive slave. The interface responds to addresses (as specified by the register Receive Cell Available Enable) by asserting the RCA corresponding to the addressed PHY when it is capable of providing a complete cell. As a result, the master selects one of the S/UNI-IMA-8's PHYs by presenting the PHY address again during the last cycle RENB is high. Had not the device been selected, RSOC, RDAT[m:0], and RPRTY would have remained high-impedance. Figure 35 illustrates that a cell transfer may be paused by deasserting RENB. The device is reselected by presenting the PHY's address the last cycle RENB is high to resume the transfer.
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Figure 35
RCLK RADR[4:0] 1F
- UTOPIA L2 Multi-PHY Receive Slave
1 Polling 2 3 4 5 Selection 6 7 8 9 10
PHY-X
1F 1 RCLK PHY-X
PHY-Y
1F 1 RCLK PHY-Y
PHY-X
1F 1 RCLK PHY-X
PHY-Z
1F 1 RCLK PHY-Z
PHY-Z
1F
RCA RDAT[m:0], RPRTY RENB RSOC Data K-3 Data K-2
PHY-Z Data 2 Data K-
Data K-1
Data K
Data 0
Data 1
13.3.4 UTOPIA L2 single-PHY Receive Slave Interface Figure 36 gives an example of the functional timing of the receive interface when configured as a single port UTOPIA L2 compliant slave. The interface responds to the address that matches the DEVID specified in the RXAPS Configuration register by asserting the RCA when it is capable of providing a complete cell. As a result, the master selects the S/UNI-IMA-8 PHYs by presenting the PHY address again during the last cycle RENB is high. Had not the device been selected, RSOC, RDAT[m:0], and RPRTY would have remained high-impedance. Figure 36 illustrates that a cell transfer may be paused by deasserting RENB. The device is reselected by presenting the PHY's address the last cycle RENB is high to resume the transfer. Figure 36 - UTOPIA L2 Single-PHY Receive Slave
16-bit Utopia L2 Single Address Slave 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Polling & Reselection Selection RCLK RADR[4:0] 1F DEVID 1F N+1 1 RCLK RCA RDAT[m:0], RPRTY RENB RSOC D(n-3) D(n-2) PAUS DEVID D(n-1) 1F N+1 D(n) DEVID 1F N+2 1 RCLK DEVID D(0) D(1) D(2) D(n-1) D(n) D(0) D(1) D(2) D(3) 1F N+3 1F N+1 1F N 1F N+1 Back 2 Back Cell
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13.3.5 Any-PHY Receive Slave Interface Figure 37 gives an example of the functional timing of the receive interface when configured as an Any-PHY compliant receive slave. The interface responds to the polling of address "IMA" (which matches the address defined by the Receive Any-PHY/UTOPIA Config register) by asserting RPA when it is capable of accepting a complete cell. The Any-PHY master repolls addresses until it receives an asserted RPA. As a result, the master re-selects the same RADR again during the last cycle RENB is high to initiate a transfer. Once transfer is initiated, RENB will remain asserted until the last data is received. Figure 37
RCLK RADR[4:0] 1F PHY-X 1F PHY-Y 1F PHY-X 2 RCLK RPA PHY-Z 2 RCLK PHY-X PHY-Y PHY-X 2 to Max -1 RDAT[m:0], RPRTY RENB RSX RSOP IMA Add Data 0 Data 1 PHY-Z 1F PHY-Z 1F PHY-Z PHY-A
- Any-PHY Receive Slave
1 2 Polling 3 4 5 Selection 6 7 8 9 10
13.4 SDRAM Interface The following three diagrams depict the timing for signals destined for the pins of the SDRAM during the Activate-Read (with Auto-precharge), Activate-Write (with Auto-precharge), and Auto-refresh command sequences and Power-Up and Initialization Sequence. The cbcmd signal is not an actual signal; it merely represents the memory access command formed by the combination of the individual SDRAM control signals (e.g., cbcsb and cbrasb). Also note that reads/writes of cell buffers are always done in bursts of eight words, with 4 bursts per cells; the first and third bursts involve the even banks and the second and fourth bursts involve the odd banks in the SDRAM.
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Figure 38
- SDRAM Read Timing
SDRAM Read Mode Timing
1 sysclk
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
cbcmd cbcsb cbrasb cbcasb cbweb cbdqm cbbs[1:0] cba[11, 9:0] cba[10] cbdq[15:0]
tRCD act0 desel/nop rd0
desel/nop
act
tRCD desel/nop rd1
desel/nop
tRCD act2 desel/nop
rd2
even bank even row even row even co prea d0 d1 odd row odd row d2 d3
odd bank odd col prea d4 d5 d6 d7 d8 d9 even row odd row
even bank even col prea
d10 d11 d12 d13 d14 d15 d16
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Figure 39
- SDRAM Write Timing
SDRAM Write Mode Timing
1 sysclk
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
cbcmd cbcsb cbrasb cbcasb cbweb cbdqm cbbs[1:0] cba[11, 9:0] cba[10] cbdq[31:0] cba[11]
act0
tRCD desel/nop
wr0
desel/nop
act1
tRCD desel/nop
wr1
desel/nop
act2
desel/nop
even bank even row even row d0 even row even co prea d1 d2 d3 d4 odd row odd row d5 d6
odd bank odd col prea d7 d8 d9 d10 odd row d11 d12
even bank even row even row d13 d14 d15 d16 even col
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Figure 40
- SDRAM Refresh
SDRAM Refresh Mode Timing
1 sysclk
2
3
4
5
6
7
8
9
10
11
12
cbcmd cbcsb cbrasb cbcasb cbweb cbdqm cbbs[1:0] cba[11:0] cbdq[15:0]
refa
tRC desel/nop
act
desel/nop
00 400h
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Figure 41
1 sysclk Vcc 2 3
- Power Up and Initialization Sequence
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
CBRI performs first arbitration on cycle following MRS
SDRAM Initialization Sequence (78 cyc) bucb_cben
REFA & tRC (9 cyc) sequence must be repeated 8 times, prior to MRS
cbcmd cbcsb cbrasb cbcasb cbweb cbdqm cbbs[1:0] cba[11:0] cbdq[15:0]
NOP
tRP (3cyc) PRE NOP
REF
NOP
REF
tRC (9cyc) NOP
MR
00 400h 033
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14
ABSOLUTE MAXIMUM RATINGS Maximum ratings are the worst case limits that the device can withstand without sustaining permanent damage. They are not indicative of normal mode operation conditions. Table 38 Absolute Maximum Ratings -40C to +85C -40C to +125C -0.3V to +3.6V -0.3V to +6.0V -0.3V to VVDDO+0.3V -0.3V to 5.5V 1000 V 100 mA 20 mA +230C +150C
Ambient Temperature under Bias Storage Temperature 1.8V Supply Voltage 3.3V Supply Voltage Voltage on Any Pin(except 5V compatible) Voltage on Any Pin( 5V compatible) Static Discharge Voltage Latch-Up Current DC Input Current Lead Temperature Absolute Maximum Junction Temperature
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15
D. C. CHARACTERISTICS TA = -40C to +85C, VDD = VDDtypical 8% (Typical Conditions: TA = 25C, VVDDI = 1.8V, VVDDO = 3.3V, VAVDDQ = 3.3V) Table 39 D.C. Characteristics
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Symbol VVDDI VVDDO VVDDQ VIL VIH VOL
Parameter Power Supply Power Supply Power Supply Input Low Voltage Input High Voltage Output or Bidirectional Low Voltage
Min 1.656 3.03 3.03 0 2.0
Typ 1.8 3.3 3.3
Max 1.944 3.56 3.56 0.8
Units Conditions Volts Volts Volts Volts Volts Guaranteed Input Low voltage. Guaranteed Input High voltage. Guaranteed output Low voltage at VDD=3.03V and IOL=maximum rated for pad. Guaranteed output High voltage at VDD=3.03V and IOH=maximum rated current for pad. Applies to RSTB and TRSTB only. Applies to RSTB and TRSTB only. Applies to RSTB and TRSTB only. VIL = GND. Notes 1 and 3. VIH = VDD. Notes 1 and 3. VIL = GND. Notes 2 and 3. VIH = VDD. Notes 2 and 3. tA=25C, f = 1 MHz tA=25C, f = 1 MHz
TBD
0.4
Volts
VOH
Output or Bidirectional High Voltage
2.4
TBD
Volts
VT+ VTVTH IILPU IIHPU IIL IIH CIN COUT
Reset Input High Voltage Reset Input Low Voltage Reset Input Hysteresis Voltage Input Low Current Input High Current Input Low Current Input High Current Input Capacitance Output Capacitance
2.0 0.8 TBD 10 -10 -10 -10 0 0 0 5 5 100 +10 +10 +10
Volts Volts Volts
A A A A pF pF
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CIO IDDOP
Bi-directional Capacitance Operating Current
5 TBD
pF mA
tA=25C, f = 1 MHz VDD = max, Outputs Unloaded
Notes on D.C. Characteristics: 1) Input pin or bi-directional pin with internal pull-up resistor. 2) Input pin or bi-directional pin without internal pull-up resistor. 3) Negative currents flow into the device (sinking), positive currents flow out of the device (sourcing).
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16
A.C. TIMING CHARACTERISTICS
(TA = -40C to +85C, VDD = 3.3 V 8%) Notes on Input Timing: 1. When a set-up time is specified between an input and a clock, the set-up time is measured from the 50% point of the input to the 50% point of the clock. 2. When a hold time is specified between a clock and an input, the hold time is measured from the 50% point of the clock to the 50% point of the input. Notes on Output Timing: 1. Output timing is measured between the 50% point of the clock to the 50% point of the output.
16.1 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS Table 40 Symbol tSAR tHAR tSALR tHALR tVL tSLR tHLR tPRD tZRD Microprocessor Interface Read Access Parameter Address to Valid Read Set-up Time Address to Valid Read Hold Time Address to Latch Set-up Time Address to Latch Hold Time Valid Latch Pulse Width Latch to Read Set-up Latch to Read Hold Valid Read to Valid Data Propagation Delay Valid Read Negated to Output Tristate Min 5 5 5 5 20 0 5 30 20 Max Units ns ns ns ns ns ns ns ns ns
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Symbol tZINTH Figure 42
Parameter Valid Read Negated to Output Tristate
Min
Max 50
Units ns
- Microprocessor Interface Read Timing
tSAR
A[10:1] tS ALR
Valid
Address
tH tH ALR
AR
tV L ALE tS (CSB+RDB)
LR
tHLR
tZ INTH INTB
tPRD D[15:0]
tZ RD
Valid Data
Notes on Microprocessor Interface Read Timing: 1. Maximum output propagation delays are measured with a 100 pF load on the Microprocessor Interface data bus (D[15:0]). 2. A valid read cycle is defined as a logical OR of the CSB and the RDB signals.
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3. In non-multiplexed address/data bus architectures, ALE should be held high so that parameters tSALR, tHALR, tVL, and tSLR are not applicable. 4. Parameter tHAR is not applicable if address latching is used. Table 41 Symbol tSAW tSDW tSALW tHALW tVL tSLW tHLW tHDW tHAW tVWR Microprocessor Interface Write Access Parameter Address to Valid Write Set-up Time Data to Valid Write Set-up Time Address to Latch Set-up Time Address to Latch Hold Time Valid Latch Pulse Width Latch to Write Set-up Latch to Write Hold Data to Valid Write Hold Time Address to Valid Write Hold Time Valid Write Pulse Width Min 5 10 5 5 20 0 5 5 5 20 Max Units ns ns ns ns ns ns ns ns ns ns
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Figure 43
- Microprocessor Interface Write Timing
A[10:1] tS ALW tV L ALE tSAW (CSB+WRB)
Valid Address
tH ALW tS LW tHLW
tVWR
tH AW
tS DW D[15:0]
tH DW
Valid Data
Notes on Microprocessor Interface Write Timing: 1. A valid write cycle is defined as a logical OR of the CSB and the WRB signals. 2. In non-multiplexed address/data bus architectures, ALE should be held high so that parameters tSALW , tSALW , tVL, tSLW and tHLW are not applicable. 3. Parameter tHAW is not applicable if address latching is used. Table 42 Symbol tVRSTB RTSB Timing Description RSTB Pulse Width Min 100 Max Units Ns
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Figure 44
- RSTB Timing tV RSTB
RSTB
16.2 Synchronous I/O Timing Figure 45
CLK Ts Input Tp Tz Output Tzb Th
- Synchronous I/O Timing
Table 43 Symbol fSYSCLK fREFCLK
SYSCLK and REFCLK Timing Description Frequency, SYSCLK Min 20 40 Max 55 60 33 40 60 Units MHz % MHz %
DSYSCLK Duty Cycle, SYSCLK Frequency, REFCLK DSYSCLK Duty Cycle, REFCLK Table 44 Symbol Ts Cell Buffer SDRAM Interface Description Input Set-up time to SYSCLK
Min 2.5
Max
Units
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Symbol Th Tp Tz Tzb
Description Input Hold time to SYSCLK SYSCLK High to Output Valid SYSCLK High to Output High-Impedance SYSCLK High to Output Driven
Min 0 1 1 1
Max
Units
10 10
Ns Ns ns
Maximum output propagation delays are measured with a 20pF load on the outputs. Minimum output propagation delays are measured with a 0 pF load on the outputs. Table 45 Symbol fCLK DCLK Ts Ts Th Tp Tz Tzb Any-PHY/UTOPIA Transmit Interface Description TCLK Frequency TCLK Duty Cycle Input Set-up time to TCLK (except TCSB) Input Set-up time to TCLK ( TCSB only) Input Hold time to TCLK TCLK High to Output Valid TCLK High to Output High-Impedance TCLK High to Output Driven 40 4 6 0 1 1 1 12 12 Min Max 52 60 % Ns Ns Ns Ns Ns Ns Units
Maximum output propagation delays are measured with an 50pF load on the outputs. Minimum output propagation delays are measured with a 0 pF load on the outputs. Table 46 Symbol fCLK Any-PHY/UTOPIA Receive Interface Description RCLK Frequency Min Max 52 Units MHz
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Symbol DCLK Ts Ts Th Tp Tz Tzb
Description RCLK Duty Cycle Input Set-up time to RCLK (except RCSB) Input Set-up time to RCLK (RCSB) Input Hold time to RCLK RCLK High to Output Valid RCLK High to Output High-Impedance RCLK High to Output Driven
Min 40 4 6 0 1 1 0
Max 60
Units % ns ns ns
12 12
ns ns ns
Maximum output propagation delays are measured with an 50pF load on the outputs. Minimum output propagation delays are measured with a 0 pF load on the outputs. Table 47 Symbol Serial Link Input Description RSCLK[7:0] Frequency (See Note 1) RSCLK[7:0] Frequency (See Note 2) RSCLK[7:0] (See Note 3) RSCLK[7:0] Duty Cycle tSRD tHRD Notes: 1. Applicable only to channelized T1 links and measured between framing bits. 2. Applicable only to channelized E1 links and measured between framing bytes. 3. Applicable only to unchannelized links of any format and measured between any two RCLK rising edges RSDATA[7:0] Set-Up Time RSDATA[7:0] Hold Time 40 5 5 Min 1.542 2.046 Max 1.546 2.05 2.304 60 Units MHz MHz MHz % Ns Ns
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Table 48 Symbol
Serial Link Output Description TSCLK[7:0] Frequency (See Note 3) TSCLK[7:0] Frequency (See Note 4) TSCLK[7:0] Frequency (See Note 5) TSCLK[7:0] Duty Cycle 40 2 Min 1.542 2.046 Max 1.546 2.05 2.304 60 27 Units MHz MHz MHz % Ns
tPTD
TSCLK[7:0] Low to TSDATA[7:0] Valid. See Note 1.
Notes on Output Timing: 1. Maximum output propagation delays are measured with a 50 pF 2. Minimum output propagation delays are measured with a 0 pF 3. Applicable only to channelized T1 links and measured between framing bits. 4. Applicable only to channelized E1 links and measured between framing bytes. 5. Applicable only to unchannelized links of any format and measured between any two TCLK rising edges
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16.3 JTAG Timing Table 49 Symbol JTAG Port Interface Description TCK Frequency TCK Duty Cycle tSTMS tHTMS tSTDI tHTDI tPTDO tVTRSTB TMS Set-up time to TCK TMS Hold time to TCK TDI Set-up time to TCK TDI Hold time to TCK TCK Low to TDO Valid TRSTB Pulse Width 40 50 50 50 50 2 100 50 Min Max 1 60 Units MHz % ns ns ns ns ns ns
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Figure 46
- JTAG Port Interface Timing
TCK tS TMS TMS tS TDI TDI tH TDI tH TMS
TCK tP TDO TDO
tV TRSTB TRSTB
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ORDERING AND THERMAL INFORMATION Table 50 Part No. PM7340-PI Table 51 Ordering and Thermal Information Description 324 Plastic Ball Grid Array (PBGA) Thermal information - Theta Ja vs. Airflow
Forced Air (Linear Feet per Minute) Conv 100 200 300
Theta JA C/Watt @ specified power Dense Board
400
500
40.3
35.9
32.9
30.8
29.5
28.5
JEDEC Board
22.4
20.7
19.5
18.7
18.1
17.6
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MECHANICAL INFORMATION 324 PIN PBGA -23x23 MM BODY - (P SUFFIX)
0 .2 0 (4X )
D D1
A1 BALL PAD CORN ER
A
0.30 M C A B 0.10 M C B
22 21 20 18 17 16 15 14 13 12 10 9 8 7 6 5 4 3 2 1 19 11
A1 BAL L CO RNER
e
A1 BALL INDICATOR
E1
E
45 CHAM F ER 4 PLACES
J I
A B C D E F G H J K L M N P R T U V W Y AA AB
b "d" DIA . 3 PLACES
TOP VIEW
C A
30 TYP
BO TT OM V IEW
bb b C
aaa C
C
A1
A2
SEATING PLA NE
SIDE VIEW
NO TE S: 1) ALL D IM ENSIO NS IN M ILLIM ET ER . 2) DIM ENSION aaa DENO TE S C O PLANA RIT Y. 3) DIM ENS IO N bbb DE NO TES PAR ALLE L.
1.82 2.03 2.22
2.07 2.28 2.49
0.40 0.50 0.60
1.12 1.17 1.22 23.00
19.00 19.50 20.20
0.30 0.36 0.40
0.55 0.61 0.67 23.00
19.00 19.50 20.20 1.00 1.00
0.50 0.63 0.70 1.00 1.00 0.15 0.35
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DETAILED REVISION HISTORY
Issue No. 3 2 1 Issue Date February, 2001 February, 2001 February, 2001 Details of Change Change made to CBA[0], CBA[1] and CBA[2] pin descriptions (Section 9.5) Change made to VDDI Pins (Section 9.9) Document Created
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NOTES
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CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com (604) 415-4533 http://www.pmc-sierra.com
Document Information: Corporate Information: Application Information: Web Site:
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 2001 PMC-Sierra, Inc. PMC-2001723 (P3) Issue date: February 2001
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